Z16C01 Datasheet, PDF (6/14 Pages) Zilog, Inc. – CPU CENTRAL PROCESSING UNIT

AC CHARACTERISTICS
No. Symbol Parameter
1
TcC
ClockCycleTime
2
TwCh
ClockWidth(High)
3
TwCl
ClockWidth(Low) -
4
TfC
ClockFallTime
5
TrC
ClockRiseTime
6
TdC(SNv) Clock+SegmenNt umbeVr alid(50pfload)
7
TdC(SNn) ClocktsegmentNumberNotValid
8
TdC(Bz) , Clockt BusFloat
9
TdC(A) ClocktAddressValid
10 TdC(Az) Clock+ AddressFloat
11 TdA(DR) AddressValidto ReadDataRequiredValid
12 TsDR(C) ReadDatato ClockFallSetupTime
13 TdDS(A) /DStAddressActive
14 TdC(DW)’ Clock+ WriteDataValid
15 ThDR(DS) ReadDatato /DS RiseHoldTime
16 TdDW(DS) WriteDataValidto /DS RiseDelay
1.7 TdAM( R) AddressValidto /MREQFallDelay
18 TdC(MR) ClockFallto /MREQFallDelay
19 TwMRh /MREQWidth(High)
20 TdMR(A) /MREQ[ AddressNotActive
21 TdDW(DSW)WriteDataValidto /DS Fall(Write)Delay
22 TdMR(DR) /MREQ[ReadDataRequiredValid
23 TdC(MR) ClockFall/MREQRiseDelay
24 TdC(ASf) Clock+ /AS FallDelay
25 TdA(AS) AddressValidto /ASRiseDelay
26 TdC(ASr) Clock[ /AS RiseDelay
27 TdASD( R) /AS + ReadDataRequiredValid
28 TdDS(AS) /DS+ /ASFallDelay
29 TwAS
/ASWidth(Low)
30 TdAS(A) /AS t AddressNotActiveDelay
31 TdAz(DSR) AddressFloatto /DS (ReadF) allDelay
32 TdAS(DSR) /AS t /DS (Read)FallDelay
33 TdDSR(DR) /DS (Read)Fallto ReadDataRequireVd alid
34 TdC(DSr) ClockFallto /OSRiseDelay
35 TdDS(DW) /DS + WriteDataNotValid
36 TdAD( SR) AddressValidto /DS(ReadF) allDelay
37 TdC(DSR) ClockRise/DS (ReadF) allDelay
38 TwDSR /DS (ReadW) idth(Low)
39 TdC(DSWj ClockFallto /DS (Write)FallDelay
40 TwDSW /DS (Write)Width(Low)
41 TdDSI(DR) /DS (l/O) [ ReadDataRequiredValid
42 TdC(DSf) Clock [ /DS (l/O)FallDelay
43 TwDS
/DS (l/O)Width(Low)
44 TdAS(DSA) /AS t /DS (AcknowledgeF)allDelay
45 TdC(DSA) Clock+ /DS (AcknowledgeF)allDelay
46 TdDSA(DR) /DS (Acknowledge[ )ReadDataRequiredDelay
47 TdC(S) ClockRiseto StatusValidDelay
216CO1/2
10 MHz
Min Max
100 **
40 **
40 **
10
10
50
0
50
50
50
180
20
45*
60
0
110*
20
50
80
20
15*
140*
50
35
20
25
140
20*
35*
30
0
35*
80
30
25*
65*
45
110*
45
75*
120*
45
160
410*
45
165*
50
6
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