Z87233 Datasheet, PDF (52/71 Pages) Zilog, Inc. – CMOS Z8-R MCU Consumer Controller Processor

Z87233
CMOS Z8“ MCU Consumer Controller Processor
46
D7–D2 Reserved
W
X Reserved—must be 0
D1–D0 STOP Mode
W
00 Stop-Mode Recovery Source 2*
00: POR only
01: AND P20, P21, P22, P23
10: AND P20, P21, P22, P23, P24, P25,
P26, P27
11: Reserved
Note: For the Stop-Mode Recovery Source, either SMR or SMR2 can be selected. If SMR2 is used
to select the Stop-Mode Recovery Source, bits D4–D2 of SMR must be 0. Not used in
conjunction with SMR Source.
Watch-Dog Timer Mode Register
The Watch-Dog Timer Mode Register, WDTMR, controls Watch-Dog Timer func-
tions. WRITE and reset states for bits D7–D0 are listed in Table 35.
Table 35. Watch-Dog Timer Mode Register—WDTMR 0Fh/R15 Bank Fh: WRITE ONLY
Bit
D7
D6 D5
D4
D3
D2
D1
D0
R/W
W
W
W
W
W
W
W
W
Reset
X
X
X
0
1
1
0
1
Note: W = Write, X = Indeterminate.
Bit
Bit
Position Field
Reset
R/W State Description
D7–D5 Reserved
W
X Reserved—must be 0
D4
X_IN
D3
WDT
W
0 X _IN Input/Internal RC Select for WDT
0: On-Board RC
1: X _IN
W
1 WDT During STOP
0: WDT disabled during STOP mode
1: WDT enabled during STOP mode
D2
WDT
W
1 WDT During HALT
0: WDT disabled during HALT mode
1: WDT enabled during HALT mode
D1–D0 WDT Tap
W
01 WDT Tap Int. RC Osc. System Clock
00:
3.5 ms
128 SCLK
01:
7 ms
256 SCLK
10:
14 ms
512 SCLK
11:
56 ms
2048 SCLK
Note: Not used in conjunction with SMR Source.
PS022701-0104