Z87233 Datasheet, PDF (35/71 Pages) Zilog, Inc. – CMOS Z8-R MCU Consumer Controller Processor

Z87233
CMOS Z8“ MCU Consumer Controller Processor
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WDTMR During STOP (D3). This bit determines whether or not the WDT is active
during STOP mode. Because the X_IN clock is stopped during STOP mode, the on-
board RC must be selected as the clock source to the POR counter. A 1 indicates
active during STOP. The default is 1.
Note: If the permanent WDT programming option is selected, the WDT
runs in all modes and cannot be stopped or disabled if the on
board RC oscillator is selected as the clock source for WDT.
Clock Source for WDT (D4). This bit determines which oscillator source is used to
clock the internal POR and WDT counter chain. If the bit is a 1, the internal RC
oscillator is bypassed and the POR and WDT clock source is driven from the
external pin, X_IN. The default configuration of this bit is 0 which selects the internal
RC oscillator.
WDTMR Register Accessibility. The WDTMR register is accessible only during the
first 64 internal system clock cycles from the execution of the first instruction after
Power-On Reset, Watch-Dog Reset, or Stop-Mode Recovery. After this point, the
register cannot be modified by any means, intentional or otherwise. The WDTMR
cannot be read and is located in Bank Fh of the Expanded Register File at
address location 0Fh (Figure 14).
Note: The WDT is permanently enabled (automatically enabled after
RESET) through a programmable option. The option is selected
when the device is programmed. In this mode, WDT is always
activated when the device comes out of RESET. Execution of
the WDT instruction serves to refresh the WDT time-out period.
WDT operation in the HALT and STOP modes is controlled by
WDTMR programming. If this option is not selected when the
device is programmed, the WDT must be activated by the user
through the WDT instruction and is always disabled by any reset
to the device.
PS022701-0104