Z86L04 Datasheet, PDF (5/26 Pages) Zilog, Inc. – Z8 8-Bit Cost-Effective Microcontrollers

Zilog
ABSOLUTE MAXIMUM RATINGS
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Parameter
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin with Respect to V_SS [Note 1]
Voltage on V_DD Pin with Respect to V_SS
Voltage on Pin 7 with Respect to V_SS [Note 2] (Z86C02/L02)
Voltage on Pin 7,8,9,10 with Respect to V_SS [Note 2] (Z86E02)
Total Power Dissipation
Maximum Allowed Current out of V_SS
Maximum Allowed Current into V_DD
Maximum Allowed Current into an Input Pin [Note 3]
Maximum Allowed Current into an Open-Drain Pin [Note 4]
Maximum Allowed Output Current Sinked by Any I/O Pin
Maximum Allowed Output Current Sourced by Any I/O Pin
Maximum Allowed Output Current Sinked by Port 2, Port 0
Maximum Allowed Output Current Sourced by Port 2, Port 0
Min
–40
–65
–0.7
–0.3
–0.7
–0.7
–600
–600
Max
+105
+150
+12
+7
V _DD+1
V _DD+1
462
300
270
+600
+600
20
20
80
80
Units
1
°C
°C
V
V
V
V
mW
mA
mA
µA
µA
mA
mA
mA
mA
Notes:
Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation of
the device at any condition above those indicated in the
operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an
extended period may affect device reliability.
Total power dissipation should not exceed 462 mW for the
package. Power dissipation is calculated as follows:
1. This applies to all pins except where otherwise noted.
2. Maximum current into pin must be ±600 µA.
There is no input protection diode from pin to V_DD.
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
Total Power dissipation = V_DD x [I_DD – (sum of I_OH)] + sum of [(V _DD – V_OH) x I_OH] + sum of (V_0L x I_0L)
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig-
ure 5).
From Output
Under Test
150 pF
Figure 5. Test Load Diagram
Capacitance
T_A = 25°C, V_CC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter
Input capacitance
Output capacitance
I/O capacitance
Min
Max
0
15 pF
0
20 pF
0
25 pF
DS97LVO0901
PRELIMINARY
5