Z86L04 Datasheet, PDF (22/26 Pages) Zilog, Inc. – Z8 8-Bit Cost-Effective Microcontrollers

Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers
Z8 CONTROL REGISTERS
R241 TMR
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
(Must be 0)
0 Disable T0 Count
1 Enable T0 Count
0 No Function
1 Load T ₁
0 Disable T _1Count
1 Enable T ₁ Count
T _IN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
Reserved (Must be 0.)
Figure 18. Timer Mode Register (F1_H: Read/Write)
R242 T1
D7 D6 D5 D4 D3 D2 D1 D0
T1 Initial Value
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T1 Current Value
(When READ)
Figure 19. Counter Timer 1 Register (f2_H:Read/Write)
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T ₁ Single Pass
1 T ₁ Modulo
Clock Source
1 T ₁ Internal
0 T1 External Timing Input
(T _IN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
Figure 20. Prescaler1 Register (F3_H: Write Only)
Zilog
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
0 Port 2 Open-Drain
1 Port 2 Push-pull
Port 3 Inputs
0 Digital Mode
1 Analog Mode
Reserved (Must be 0)
Figure 22. Port 3 Mode Register (F7_H: Write Only)
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
P0₃-P0₀ Mode
00 = Output
01 = Input
Reserved (Must be 1.)
Reserved (Must be 0.)
Figure 23. Port 0 and 1 Mode Register
(F8_H: Write Only)
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved (Must be 0.)
Figure 24. Interrupt Priority Register
(F9_H: Write Only)
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
P2 ₇ - P20 I/O Definition
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
Figure 21. Port 2 Mode Register (F6_H: Write Only)
22
PRELIMINARY
DS97LVO0901