Z86C95 Datasheet, PDF (2/18 Pages) Zilog, Inc. – CMOS Z8 DIGITAL SIGNAL PROCESSOR (DSP)

Z86C95 DSP
CPS DC-4067-13
GENERAL DESCRIPTION (Continued)
2. ICC2 at STOP Mode and DSP Pause will show a
current of 1-2 mA, then will jump to 5-7 mA, and will
settle at 3-4 mA. Settling time is about 10-15 seconds.
3. The zero error for the ADC at 25°C is about 180 mV.
Output Input
Vcc
GND
XTAL /AS /DS R//W /RESET /WAIT
Port 3
SPI
UART
Three 16-Bit
Counter/
Timers
32 ÷ 16
Divider
16 x 16
Multiplier
Interrupt
Control
ALU
Flags
Register
Pointer
Register File
256 x 8-Bit
Machine Timing and
Instruction Control
Program
Counter
Digital Signal Processor
DSP RAM
Bank 1
DSP RAM
Bank 2
Program
RAM
Port 2
I/O
(Bit Programmable)
Address
A15-A0*
* In multiplexed mode,
A7-A0 reflects the DSP
address bus for emulation.
AD7-AD0
8
Address/Data
ADC
8 Channel
Analog In
DAC
Analog
Out
PWM
PWM
Functional Block Diagram
2