Z86C95 Datasheet, PDF (11/18 Pages) Zilog, Inc. – CMOS Z8 DIGITAL SIGNAL PROCESSOR (DSP)

AC CHARACTERISTICS
External I/O or Memory Read and Write; DSR/DSW; WAIT Timing Table
No Sym
Parameter
T_A = 0°C to +70°C
40 MHz**
33 MHz
24 MHz
Min Max Min Max Min Max
1 TdA(AS)
Address Valid To /AS Rise Delay
8
2 TdAS(A)
/AS Rise To Address Hold Time
15
3 TdAS(DI)
/AS Rise Data In Req’d Valid Delay
4 TwAS
/AS Low Width
10
5 TdAZ(DSR) Address Float To /DS Fall (Read)
0
6 TwDSR
/DS (Read) Low Width
60
7 TwDSW
/DS (Write) Low Width
35
8 TdDSR(DI) /DS Fall (Read) To Data Req'd Valid Delay
9 ThDSR(DI) /DS Rise (Read) to Data In Hold Time
0
10 TdDS(A)
/DS Rise To Address Active Delay
20
11 TdDS(AS)
/DS Rise To /AS Delay
16
12 TdR/W(AS) R/W To Valid /AS Rise Delay
10
13 TdDS(R/W) /DS Rise To R/W Not Valid Delay
12
14 TdDO(DSW) Data Out To /DS Fall (Write) Delay
12
15 ThDSW(DO) /DS Rise (Write) To Data Out Hold Time 12
16 TdA(DI)
Address Valid To Data Req’d Valid Delay
17 TdAS(DSR) /AS Rise To /DS Fall (Read) Delay
20
19 TdDM(AS)
/DM Valid To /AS Rise Delay
10
20 TdDS(DM) /DS Rise To /DM Valid Delay
15
21 ThDS(A)
/DS Rise To Address Valid Hold Time
15
22 TdXT(SCR) XTAL Falling to SCLK Rising
23 TdXT(SCF) XTAL Falling to SCLK Falling
24 TdXT(DSRF) XTAL Falling to/DS Read Falling
25 TdXT(DSRR) XTAL Falling to /DS Read Rising
26 TdXT(DSWF) XTAL Falling to /DS Write Falling
27 TdXT(DSWF) XTAL Falling to /DS Write Rising
28 TsW(XT)
Wait Set-up Time
5
29 ThW(XT)
Wait Hold Time
15
30 TwW
Wait Width (One Wait Time)
20
15
20
75
15
0
65
40
40
0
25
16
12
12
12
12
90
20
10
15
15
30
30
40
30
40
30
5
15
20
22
25
96
130
28
0
100
65
45
80
0
40
30
26
30
34
34
115
160
40
22
35
30
35
40
35
40
45
50
35
45
45
50
35
45
5
15
25
Notes:
When using extended memory timing add 2 TpC.
Timing numbers given are for minimum TpC.
** Preliminary values, to be characterized.
Z86C95 DSP
CPS DC-4067-13
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11