Z8523316VSG Datasheet, PDF (2/4 Pages) Zilog, Inc. – EMSCC™ Enhanced Mono Serial Communication Controller

Z85233 EMSCC™ Enhanced Mono Serial Communication Controller
automatically: transmit a flag before the data, reset
the Tx Underrun/EOM latch, force the TxD pin
high at the appropriate time when using NRZI
encoding, deassert the /RTS pin after the closing
flag, and better handle ABORTed frames when
using the 10x19 status FIFO. The combination of
these features along with the deeper data FIFOs
significantly simplifies SDLC driver software.
The CPU hardware interface has been simplified
by relieving the databus setup time requirement
and supporting the software generation of the inter-
rupt acknowledge signal (/INTACK). These
changes allow an interface with less external logic
to many microprocessor families while maintain-
ing compatibility with existing designs. I/O han-
dling of the EMSCC is improved over the SCC
with faster response of the /INT and /DTR//REQ
pins.
The many enhancements added to the EMSCC per-
mits a system design that increases overall system
performance with better data handling and less
interface logic.
Note: All Signals with a preceding front
slash, "/", are active Low, e.g.: B//W
(WORD is active Low); /B/W (BYTE
is active Low, only).
Power connections follow conventional descrip-
tions below:
Connection
Power
Ground
Circuit
V_CC
GND
Device
V_DD
V_SS
Databus
Control
CPU & DMA
Bus Interface
Interrupt
Control
/INT
/INTACK
IEI
IEO
Internal
Control
Logic
Channel A
R egis ter
Interrupt
Control
Logic
Channel B
R egis ter
Channel A
Channel B
Figure 1. Z85233 Functional Block Diagram
PB005802-0608
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