Z8523316VSG Datasheet, PDF (1/4 Pages) Zilog, Inc. – EMSCC™ Enhanced Mono Serial Communication Controller

EMSCC™ Enhanced Mono Serial Communication Controller
Z85233
Product Brief
PB005802-0608
FEATURES
• Hardware and software compatible with
Zilog's SCC/ ESCC™
• Deeper Data FIFOs
– 4-Byte Transmit FIFO
– 8-Byte Receive FIFO
• Programmable FIFO Interrupt Levels Provide
Flexible Interrupt Response
• Many Improvements toSupport SDLC/
HDLCTransfers:
– Deactivation of /RTS Pin after Closing
Flag
– Automatic Transmission of the Opening
Flag
– Automatic Reset of Tx Underrun/EOM
Latch
– Complete CRC Reception
– TxD pin Automatically Forced High with
NRZI Encoding when Using Mark Idle.
– Receive FIFO Automatically Unlocked for
Special Receive Interrupts when Using the
SDLC Status FIFO.
– Back-to-Back Frame Transmission Simpli-
fied
• Easier Interface to Popular CPUs
• Fast Speeds:
– 10.0 MHz for Data Rates up to 2.5 Mbit/
Sec.
– 16.384 MHz for Data Rates up to 4.096
Mbit/Sec. -20.0 MHz for Data Rates up to
5.0 Mbit/Sec.
• Improved SDLC Frame Status FIFO
• Low Power CMOS
• New Programmable Features Added with
Write Register 7'
• Write registers: WR3, WR4, WR5, and WR10
are Now Readable
• Read Register 0 Latched During Access
• Software Interrupt Acknowledge Mode
• DPLL Counter Output Available as Jitter-Free
Clock Source
• /DTR//REQ Pin Deactivation Time Reduced
• A Full-Duplex Channel with a Crystal Oscilla-
tor, Baud Rate Generator, and Digital Phase-
Locked Loop.
• Multi-Protocol Operation Under Program Con-
trol
• Asynchronous Mode/Synchronous Mode
GENERAL DESCRIPTION
The Zilog Enhanced Mono Serial Communication-
Controller, Z85233 EMSCC, is a software compat-
ible CMOS member of the SCC family introduced
by Zilog in 1981. The EMSCC is a full-duplex data
communications controller capable of supporting a
wide range of popular protocols. The Z85233
EMSCC is a single channel version (Channel A) of
Zilog's Z85230 ESCC. Based on Zilog's unique
Superintegration™ Technology, the EMSCC is
compatible with designs using Zilog's SCC and
ESCC to receive and transmit data. It has many
improvements that significantly reduce CPU over-
head. The addition of a 4-byte transmit FIFO and
an 8-byte receive FIFO significantly reduces the
overhead required to provide data to, and get data-
from, the transmitter and receiver.
The EMSCC also has many features that improve
packet handling in SDLC mode. The EMSCC will
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