Z8623012SSG Datasheet, PDF (11/61 Pages) Zilog, Inc. – ADVANCED PROGRAM BLOCKING AND NTSC LINE 21 XDS DECODER

BLOCK DIAGRAM AND OPERATIONAL OVERVIEW
ARCHITECTURAL OVERVIEW
1.1.1 Input Signals
The Composite Video input should be a signal which is nominally 1.0 Volt p-p,
with sync tips negative and band limited to 600 kHz. The Z86230 operates with an
input level variation of ±3 dB.
The HIN/XIN input signal is required to bring the voltage-controlled oscillator
(VCO) close to the required operating frequency.
1.1.2 Video Input Signal Processing
The Composite Video input is AC-coupled to the device where the sync tip is
internally clamped to a fixed reference voltage.
The Data Slicer extracts a clean CMOS-level data signal by slicing the signal at its
midpoint. The slice level is established on an adaptive basis during Line 21.
The Sync Slicer processes the clamped Composite Video signal to extract Com-
posite Sync. This signal is used to lock the internal logic to the incoming video.
The slice level is stored on the sync slice capacitor, CSYNC.
The Data Clock Recovery circuit operates in conjunction with the Horizontal (H)
Lock circuit. These circuits produce a data clock (DCLK) and, when Line 21 code
appears, DCLK phase lock is achieved during the clock run-in burst (used to
reclock the sliced data). When phase lock is established, DCLK is maintained until
a change in the video signal occurs.
1.1.3 Voltage-Controlled Oscillator (VCO) and One-Shot
All internal timing and synchronizing signals are derived from the on-board 12-
MHz VCO. Its output is the DCLK signal used to drive the Horizontal and Vertical
counter chains.
The One-Shot circuit produces a horizontal timing signal derived from the incom-
ing video.
The VCO exhibits stable gain characteristics and good power supply rejection.
1.1.4 Timing and Counting Circuits
The DCLK is divided to generate the horizontal timing signals H and 2H.The H
signal is further divided in the line counter (LINE CNTR) and field counter (FLD
CNTR) to produce the various decodes used to establish vertical lock and to time
the control functions required for proper operation.
1.1.5 Command Processor
The Command Processor controls the manipulation of the data for storage. During
the recovery time, the command processor, in conjunction with the data recovery
circuits, recovers the XDS data.
PS000401-TVC0699
Z86230—PRELIMINARY
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