ZBNG4000 Datasheet, PDF (7/10 Pages) Zetex Semiconductors – FET BIAS CONTROLLER

ZNBG4000 ZNBG4001
ZNBG6000 ZNBG6001
APPLICATIONS INFORMATION (Continued)
The ZNBG devices have been designed to protect the external FETs from adverse operating
conditions. With a JFET connected to any bias circuit, the gate output voltage of the bias circuit
can not exceed the range -3.5V to 0.7V, under any conditions including powerup and powerdown
transients. Should the negative bias generator be shorted or overloaded so that the drain current
of the external FETs can no longer be controlled, the drain supply to FETs is shut down to avoid
damage to the FETs by excessive drain current.
The following diagrams show the ZNBG4000/1 and ZNBG6000/1 in typical LNB applications.
Within each FET gain stage the numbering system indicates how the bias stages relate to the
application circuits. This is important when RCAL values are used to set differing drain currents.
Dual standard or enhanced LNB block diagram
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