PSN1720A_07 Datasheet, PDF (1/2 Pages) Z-Communications, Inc – PHASE LOCKED LOOP

9939 Via Pasar • San Diego, CA 92126
TEL [phone] FAX [phone]
PSN1720A
PHASE LOCKED LOOP
Rev A1
PHASE NOISE (1 Hz BW, typical)
0
-40
-80
FEATURES
• Frequency Range: 1690 - _{1760 MHz}
• Step Size:
50 _KHz
• _PLL - Style Package
APPLICATIONS
• Telecommunications
• Satellite
• ^Telemetry
-120
-160
-200
100 Hz
1 kHz
10 kHz
100 kHz
PERFORMANCE SPECIFICATIONS
Frequency Range
VALUE
1690 - 1760
Phase Noise @ 10 kHz offset (1 Hz BW, typ.)
-104
Harmonic Suppression (2nd, typ.)
-15
Sideband Spurs (typ.)
-70
Power Output
3.5±2.5
Load Impedance
50
Step Size
50
Charge Pump Output Current
1000
Switching Speed (typ., adjacent channel)
Startup Lock Time (typ.)
Operating Temperature Range
4
6
-40 to 85
Package Style
PLL
POWER SUPPLY REQUIREMENTS
Supply Voltage (Vcc, nom.)
5
Supply Current (Icc, typ.)
33
All specifications are typical unless otherwise noted and subject to change without notice.
UNITS
MHz
dBc/Hz
dBc
dBc
dBm
KHz
mSec
mSec
°C
Vdc
mA
APPLICATION NOTES
• AN-107 : How to Solder Z-COMM VCOs / PLLs
• AN-200 : Mounting and Grounding of Z-COMM PLLs
• AN-201 : PLL Fundamentals
AN-202 : PLL Functional Description
NOTES:
Reference Oscillator Signal: 5 MHz< <40 MHz
Frequency Synthesizer: National Semiconductor - LMX2326
© Z-Communications, Inc.
Page 1
All rights reserved