ZL50022 Datasheet, PDF (98/121 Pages) Zarlink Semiconductor Inc – Enhanced 4 K Digital Switch with Stratum 4E DPLL

ZL50022
Data Sheet
AC Electrical Characteristics^† - JTAG Test Port Timing
Characteristic
Sym. Min.
1 TCK Clock Period
t_TCKP
100
2 TCK Clock Pulse Width High
t_TCKH
20
3 TCK Clock Pulse Width Low
t_TCKL
20
4 TMS Set-up Time
t_TMSS
10
5 TMS Hold Time
t_TMSH
10
6 TDi Input Set-up Time
t_TDIS
20
7 TDi Input Hold Time
t_TDIH
60
8 TDo Output Delay
t_TDOD
9 TRST pulse width
t_TRSTW
200
† Characteristics are over recommended operating conditions unless otherwise stated.
Typ.
Max.
30
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
C_L = 30 pF
TCK
TMS
t_TMSS
t_TCKL
t_TCKH
t_TCKP
t_TMSH
TDi
TDo
TRST
t_TDIS
t_TDIH
t_TDOD
t_TRSTW
Figure 30 - JTAG Test Port Timing Diagram
AC Electrical Characteristics^† - OSCi 20 MHz Input Timing
Characteristic
Sym. Min. Typ. Max.
1 Input frequency accuracy
-32
32
-100
100
2 Duty cycle
40
60
3 Input rise or fall time
t_IR,t_IF
3
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ See “Performance Characteristics Notes” on page 118.
Units
ppm
ppm
%
ns
Notes^‡
Stratum 4E
Relaxed Stratum 4E
1
14
98
Zarlink Semiconductor Inc.