ZL50021_0611 Datasheet, PDF (96/136 Pages) Zarlink Semiconductor Inc – Enhanced 4 K Digital Switch with Stratum 3 DPLL

ZL50021
Data Sheet
External Read/Write Address: 0120_H - 013F_H
Reset Value: 0000_H
15 14 13 12
11
10
9
0
0
0
0 STIN[n] STIN[n] STIN[n]
Q3C2
Q3C1
Q3C0
8
STIN[n]
Q2C2
7
STIN[n]
Q2C1
6
STIN[n]
Q2C0
5
STIN[n]
Q1C2
4
STIN[n]
Q1C1
3
STIN[n]
Q1C0
2
STIN[n]
Q0C2
1
STIN[n]
Q0C1
0
STIN[n]
Q0C0
Bit
15 - 12
11 - 9
8-6
Name
Description
Unused
Reserved. In normal functional mode, these bits MUST be set to zero.
STIN[n]Q3C2 - 0
Quadrant Frame 3 Control Bits. These three bits are used to control STi[n]’s
quadrant frame 3, which is defined as Ch24 to 31, Ch48 to 63, Ch96 to 127 and
Ch192 to 255 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps
modes respectively.
STIN[n]Q3C
2-0
0xx
100
101
110
111
Operation
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
STIN[n]Q2C2 - 0
Quadrant Frame 2 Control Bits. These three bits are used to control STi[n]’s
quadrant frame 2, which is defined as Ch16 to 23, Ch32 to 47, Ch64 to 95 and
Ch128 to 191 for the 2.048 Mbps, 4.096 Mbps, 8.192 Mbps, and 16.384 Mbps
modes respectively.
STIN[n]Q2C
2-0
0xx
100
101
110
111
Operation
normal operation
LSB of each channel is replaced by “0”
LSB of each channel is replaced by “1”
MSB of each channel is replaced by “0”
MSB of each channel is replaced by “1”
Table 62 - Stream Input Quadrant Frame Register 0 - 31 (SIQFR0 - 31) Bits
96
Zarlink Semiconductor Inc.