ZL50021_0611 Datasheet, PDF (20/136 Pages) Zarlink Semiconductor Inc – Enhanced 4 K Digital Switch with Stratum 3 DPLL

ZL50021
Data Sheet
PBGA Pin
Number
M13
LQFP Pin
Number
41
P10
43
G2
211
Pin Name
MOT_INTEL
IRQ
RESET
Description
Motorola_Intel (5 V-Tolerant Input with Internal Pull-up) This
pin selects the Motorola or Intel microprocessor interface to be
connected to the device. When this pin is unconnected or
connected to high, Motorola interface is assumed. When this pin is
connected to ground, Intel interface should be used.
Interrupt (5 V-Tolerant Three-state Output): This programmable
active low output indicates that the internal operating status of the
DPLL has changed. An external pull-up resistor MUST hold this
pin at HIGH level.
Device Reset (5 V-Tolerant Input with Internal Pull-up) This
input (active LOW) puts the device in its reset state that disables
the STio0 - 31 drivers and drives the STOHZ0 - 15 outputs to high.
It also preloads registers with default values and clears all internal
counters. To ensure proper reset action, the reset pin must be low
for longer than 1 µs. Upon releasing the reset signal to the device,
the first microprocessor access cannot take place for at least
600 µs due to the time required to stabilize the device and the
crystal oscillator from the power-down state. Refer to Section
Section 17.2 on page 49 for details.
3.0 Device Overview
The device has thirty-two ST-BUS/GCI-Bus inputs (STi0 - 31) and thirty-two ST-BUS/GCI-Bus outputs (STio0 - 31).
STio0 - 31 can also be configured as bi-directional pins, in which case STi0 - 31 will be ignored. It is a non-blocking
digital switch with 4096 64 kbps channels and is capable of performing rate conversion between ST-BUS/GCI-Bus
inputs and ST-BUS/GCI-Bus outputs. The ST-BUS/GCI-Bus inputs accept serial input data streams with data rates
of 2.048, 4.096, 8.192 and 16.384 Mbps on a per-stream basis. The ST-BUS/GCI-Bus outputs deliver serial data
streams with data rates of 2.048, 4.096, 8.192 and 16.384 Mbps on a per-stream basis. The device also provides
sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external ST-BUS/GCI-Bus tristate
drivers for the first sixteen ST-BUS/GCI-Bus outputs (STio0 -15).
By using Zarlink’s message mode capability, microprocessor data stored in the connection memory can be
broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and status
information for external circuits or other ST-BUS/GCI-Bus devices.
The device uses the ST-BUS/GCI-Bus input frame pulse (FPi) and the ST-BUS/GCI-Bus input clock (CKi) to define
the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates. The
output data streams will be driven by and have their timing defined by FPi and CKi in Divided Slave mode. In
Multiplied Slave mode, the output data streams will be driven by an internally generated clock, which is multiplied
from CKi internally. In Master mode, the on-chip DPLL will drive the output data streams and provide output clocks
and frame pulses. Refer to Application Note ZLAN-120 for further explanation of the different modes of operation.
When the device is in Master mode, the DPLL is phase-locked to one of four DPLL reference signals, REF0 - 3,
which are sourced by an external 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or
19.44 MHz reference signal. The on-chip DPLL also offers jitter attenuation, reference switching, reference
monitoring, freerun and holdover functions. The jitter performance exceeds the Stratum 3 specification. The intrinsic
jitter of all output clocks is less than 1 ns (except for the 1.544 MHz output).
There are two slave modes for this device:
The first is the Divided Slave mode. In this mode, output streams are clocked by input CKi. Therefore the output
streams have exactly the same jitter as the input streams. The output data rate can be the same as or lower than
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