ZL50119 Datasheet, PDF (80/95 Pages) Zarlink Semiconductor Inc – 32, 64 and 128 Channel CESoP Processors

12.6.5 TBI Interface Timing
ZL50115/16/17/18/19/20
Parameter
GTXCLK period
GTXCLK high wide time
GTXCLK low wide time
TXD[9:0] Output Delay
(GTXCLK rising edge)
RCB0/RBC1 period
RCB0/RBC1 high wide time
RCB0/RBC1 low wide time
RCB0/RBC1 rise time
RCB0/RBC1 fall time
RXD[9:0] setup time (RCB0
rising edge)
RXD[9:0] hold time (RCB0
rising edge)
REFCLK period
REFCLK high wide time
REFCLK low wide time
Symbol
t_GC
t_GH
t_GL
t_DV
Min.
7.5
2.5
2.5
1
1000 Mbps
Typ.
-
-
-
-
Max.
8.5
-
-
6
t_RC
15
16
17
t_RH
5
-
-
t_RL
5
-
-
t_RR
-
-
2
t_RF
-
-
2
t_DS
2
-
-
t_DH
1
-
-
t_FC
7.5
-
8.5
t_FH
2.5
-
-
t_FL
2.5
-
-
Table 34 - TBI Timing - 1000 Mbps
Data Sheet
Units
Notes
ns
ns
ns
Load = 25 pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_GC
GTXCLK
t_DV
TXD[9:0] /I/ /S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/
Signal_Detect
Figure 36 - TBI Transmit Timing Diagram
80
Zarlink Semiconductor Inc.