ZL50119 Datasheet, PDF (27/95 Pages) Zarlink Semiconductor Inc – 32, 64 and 128 Channel CESoP Processors

ZL50115/16/17/18/19/20
Data Sheet
Signal
I/O
Package Balls
Description
TDM_STo[3:0]
OT [3] M2
[2] N1
[1] R4
[0] V1
TDM port serial data output streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STo[3:0]
H.110: TDM_D[3:0]
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
stream [0] is used. Stream [0] is used for
unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
TDM_CLKi[3:0]
I D [3] M1
[2] P1
[1] T1
[0] R3
TDM port clock inputs programmable as
active high or low. Can accept frequencies of
1.544 MHz, 2.048 MHz, 4.096 MHz,
8.192 MHz, 6.312 MHz or 16.384 MHz
depending on standard used. At 8.192 Mbps
only stream [0] is used. Stream [0] is used
for unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
TDM_CLKo[3:0]
OT [3] N2
[2] R1
[1] T2
[0] V2
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz or 16.384 MHz
depending on standard used. At 8.192 Mbps
only stream [0] is used. Stream [0] is used
for unstructured J2, T3/E3 or STS-1 on the
ZL50117/20.
Table 3 - TDM Interface Stream Pin Definition
Note: Speed modes:
2.048 Mbps - 32 channels per stream.
8.192 Mbps - 128 channels per stream.
J2 - 98 channels per stream
E3 - 537 channels per stream
T3 - 699 channels per stream
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
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Zarlink Semiconductor Inc.