MT90222 Datasheet, PDF (80/155 Pages) Zarlink Semiconductor Inc – 4/8/16 Port IMA/TC PHY Device

MT90222/3/4
Data Sheet
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
15:13
12:8
7:5
4:0
Type
R
R/W
R
R/W
0x0040-0x0047 (8 reg)
1 register per 2 links in non-IMA mode. Link 0 is paired with link 8, link 1 with link
9 and so on
0000
Description
Unused. Read all 0’s.
UTOPIA PHY Address of Link N+8 when in non-IMA mode.
Unused. Read all 0’s.
UTOPIA PHY Address of Link N when in non-IMA mode.
Table 12 - UTOPIA Input Link Address Registers
Address (Hex):
Direct access
Reset Value (Hex):
0x0048-0x004B (4 reg)
1 register per 2 IMA Groups. IMA group 0 is paired with IMA group 4, IMA group 1
with IMA group 5 and so on. For MT90222 only groups 0, 1, 2 and 3 are used.
0000
Bit #
15:13
12:8
7:5
4:0
Type
R
R/W
R
R/W
Description
Unused. Read all 0’s.
UTOPIA PHY Address of IMA Group N+4.
Unused. Read all 0’s.
UTOPIA PHY Address of IMA Group N.
Table 13 - UTOPIA Input Group Address Registers
Address (Hex):
Direct access
Reset Value (Hex):
0x0050 (1 reg)
1 register to enable the links in non-IMA mode.
0000
Bit # Type
Description
15
R/W Enable UTOPIA PHY address of link 15. A 1 enables the PHY port Address, non-IMA
mode.
14
R/W Enable UTOPIA PHY address of link 14. A 1 enables the PHY port Address, non-IMA
mode.
...
...
...
1
R/W Enable UTOPIA PHY address of link 1. A 1 enables the PHY port Address, non-IMA mode.
0
R/W Enable UTOPIA PHY address of link 0. A 1 enables the PHY port Address, non-IMA mode.
Table 14 - UTOPIA Input Link PHY Enable Register
80
Zarlink Semiconductor Inc.