MT90222 Datasheet, PDF (55/155 Pages) Zarlink Semiconductor Inc – 4/8/16 Port IMA/TC PHY Device

MT90222/3/4
Data Sheet
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings.
Data rate (bits 6:5) = 01
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 1
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
4.2 Wire-OR Mode
In this mode, two or four links are logically OR’ed together to share a single stream. This is particularly useful for
fractional T1/E1 applications where links using different time slots can be multiplexed together onto a single stream
in order to facilitate the interface to a single T1 or E1 framer.
Links that are OR’ed together can have any one of the Single mode discussed in Section 4.1. To avoid any
contention, mapping registers of those links must not have the same bit set.
All links in Wire-OR mode must be configured in the same as they were in Single mode, except for TDM Link Control
registers. Two minor modes are available, 2-link grouping and 4-link grouping.
4.2.1 Wire-OR Mode - 2 Link Grouping
Two links in a pair are OR’ed together by using this mode. The links that are paired are pre-determined: link 0 is
paired with link 1, link 2 is paired with link 3 and so on. When link 0 and link 1 are paired, the pins associated with
link 1 cannot be used and are tri-stated, however, bit 7 of its TDM TX(RX) Link Control registers must be set. The
two links operate using the Clock and SYNC signals of link 0. The same logic applies for the other pairs.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings. Note that both links in a pair must have the same settings.
Data rate (bits 6:5) = 00 or 01
Multiplex mode (bits 4:3) = 01
Clock and Sync format (bit 2) = 0 or 1
Enable (bit 7) = 1
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
4.2.2 Wire-OR Mode - 4 Link Grouping
Four links in a group are OR’ed together by using this mode. The links that are grouped are pre-determined: links 0,
1, 2 and 3 are grouped and the OR’ed input/output is available on link 0 only. Pins associated with links 1, 2 and 3
cannot be used and are tri-stated, however, bit 7 of TDM TX(RX) Link Control registers for those three links must
be set. The four links operate using the Clock and SYNC signal of link 0. The same logic applies for the other groups.
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
the following settings. Note that all four links in a group must have the same settings.
Data rate (bits 6:5) = 00 or 01
Multiplex mode (bits 4:3) = 10
Clock and Sync format (bit 2) = 0 or 1
Enable (bit 7) = 1
Cell delineation mode (bit 10 of TDM RX Link Control only) = 0
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Zarlink Semiconductor Inc.