ZL30410_06 Datasheet, PDF (8/39 Pages) Zarlink Semiconductor Inc – Multi-service Line Card PLL

Pin Description (continued)
Pin #
Name
36
Tclk
37
Trst
38
Tdi
39
NC
40
NC
41
PRIOR
42
C1.5o
43
C6o
44
IC
45
GND
46
C19o
47
RefSel
48
RefAlign
49
VDD
50
NC
51
C20i
52
GND
ZL30410
Data Sheet
Description
IEEE1149.1a Test Clock Signal (5 V tolerant input). Input clock for the JTAG
test logic. If not used, this pin should be pulled up to VDD.
IEEE1149.1a Reset Signal (3.3 V input). Asynchronous reset for the JTAG
TAP controller. This pin should be pulsed low on power-up to ensure that the
device is in the normal functional state. This pin is internally pulled up to VDD.
If this pin is not used then it should be connected to GND.
IEEE1149.1a Test Data Input (3.3 V input). Input for JTAG serial test
instructions and data. This pin is internally pulled up to VDD. If not used, this
pin should be left unconnected.
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Primary Reference Out of Range (Output). Logic high at this pin indicates
that the Primary Reference is off the PLL centre frequency by more than
±12 ppm. See PRIOR pin description in Section 4.2 on page 17 for details.
Clock 1.544 MHz (CMOS tristate output). This output provides a 1.544 MHz
DS1 rate clock.
Clock 6.312 MHz (CMOS tristate output). This output provides a 6.312 MHz
DS2 rate clock.
Internal Connection. Connect this pin to Ground.
Ground
Clock 19.44 MHz (CMOS tristate output). This output provides a 19.44 MHz
clock.
Reference Source Select (Input). A logic low selects the PRI (primary)
reference source as the input reference signal and logic high selects the SEC
(secondary) input. The logic level at this input is sampled at the rising edge of
F8o. This pin is internally pulled down to GND.
Reference Alignment (Input). In Hardware Control pulling this pin low for
250 µs initiates phase realignment between the input reference and the
generated output clocks. See Section 3.2.4 on page 11 for details. This pin
should never be tied low permanently. Internally this pin is pulled down to
GND.
Positive Power Supply
No internal bonding Connection. Leave unconnected.
Clock 20 MHz (5 V tolerant input). This pin is the input for the 20 MHz Master
Clock Oscillator. The clock oscillator should be connected directly (not AC
coupled) to the C20i input and it must supply clock with duty cycle that is not
worse than 40/60%.
Digital Ground
8
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