ZL30410_06 Datasheet, PDF (17/39 Pages) Zarlink Semiconductor Inc – Multi-service Line Card PLL

ZL30410
Data Sheet
FCS pin: Filter Characteristic Select. The FCS (pin 9) input is used to select the filtering characteristics of the
Core PLL. See Table 2 on page 17 for details.
FCS
Filtering Characteristic
0 Filter corner frequency set to 12 Hz.
This selection meets loop filter characteristics for line card applications
1 Filter corner frequency set to 6 Hz.
This selection meets requirements of G.813 Option 1
Table 2 - Filter Characteristic Selection
Phase Slope
Limit
N/A
41 ns
in 1.326 ms
RefSel: Reference Source Select. The RefSel (pin 47) input selects the PRI (primary) or SEC (secondary) input
as the reference clock for the Core PLL. The logic level at this input is sampled by the rising edge of F8o.
RefSel
0
1
Input Reference
Core PLL connected to the Primary Acquisition PLL
Core PLL connected to the Secondary Acquisition PLL
Table 3 - Reference Source Select
RefAlign: Reference Alignment. The RefAlign (pin 48) input controls phase realignment between the input
reference and the generated output clocks. See Section 3.2.4 on page 11 for details.
4.2 Status Pins
The ZL30410 has four dedicated status pins for indicating modes of operation and quality of the Primary and
Secondary reference clocks. These pins are listed below:
LOCK. This output goes high after the ZL30410 has completed its locking sequence (see section 2.2.3 for details).
HOLDOVER - This output goes high when the Core PLL enters Holdover mode. The Core PLL will switch to
Holdover mode if the respective Acquisition PLL enters Holdover mode or if the mode select pins are set to
Holdover (MS2, MS1 = 01).
PRIOR - (Primary Reference Out of Range). The PRIOR status is based on two detectors that monitor reference
quality with different precision and response times. Outputs of both detectors are combined together (OR function)
to drive PRIOR status pin.
This output goes high when one of the detectors is triggered by the failing Primary Reference clock:
• Slow Response Detector (High Precision): This detector detects if the primary reference is off its nominal
frequency by more than ±12 ppm. The frequency offset monitor updates internally every 10 sec and will
change state after two matching measurements (PASS/PASS or FAIL/FAIL). This is in full compliance with
the GR-1244-CORE requirement of 10 to 30 sec Reference Validation Time. This output returns to zero
when the reference frequency is requalified within ±9.2 ppm of the nominal frequency (monitor circuit has
built-in hysteresis). In an extreme case, when over time the Master Clock oscillator drifts ±4.6 ppm the
switching thresholds will change as well, as is shown in Figure 7.
• Fast Response Detector (Low Precision): This detector detects a large frequency offset (greater than 3%) or
large change in a single cycle period (grater than 30%). In both cases detector will almost instantaneously
(in less than 250 µs) disqualify the reference and reset the 10 sec internal timer.
SECOR - (Secondary Reference Out of Range). Functionally, this pin is equivalent to the PRIOR pin for Primary
Acquisition PLL.
17
Zarlink Semiconductor Inc.