ZL50110 Datasheet, PDF (73/103 Pages) Zarlink Semiconductor Inc – 128, 256 and 1024 Channel CESoP Processors

ZL50110/11/14
Data Sheet
11.0 AC Characteristics
11.1 TDM Interface Timing - ST-BUS
The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device
sourcing the data, or Master mode, where the TDM clocks are generated from the ZL50110/11/14.
11.1.1 ST-BUS Slave Clock Mode
TDM ST-BUS Slave Timing Specification
Data Format
ST-BUS
8.192 Mbps
mode
ST-BUS
2.048 Mbps
mode
All Modes
Parameter
TDM_CLKi Period
TDM_CLKi High
TDM_CLKi Low
TDM_CLKi Period
TDM_CLKi High
TDM_CLKi Low
TDM_F0i Width
8.192 Mbps
2.048 Mbps
Symbol
t_C16IP
t_C16IH
t_C16IL
t_C4IP
t_C4IH
t_C4IL
t_FOIW
TDM_F0i Setup Time t_FOIS
Min.
54
27
27
-
110
110
50
200
5
TDM_F0i Hold Time
t_FOIH
5
TDM_STo Delay
t_STOD
1
TDM_STi Setup Time t_STIS
5
TDM_STi Hold Time
t_STIH
5
Typ.
60
-
-
244.1
-
-
-
-
-
-
-
-
-
Max.
66
33
33
-
134
134
-
300
-
-
20
-
-
Units
ns
ns
ns
ns
ns
ns
ns
Notes
ns With respect to
TDM_CLKi
falling edge
ns With respect to
TDM_CLKi
falling edge
ns With respect to
TDM_CLKi
Load C_L = 50 pF
ns With respect to
TDM_CLKi
ns With respect to
TDM_CLKi
73
Zarlink Semiconductor Inc.