ZL50110 Datasheet, PDF (36/103 Pages) Zarlink Semiconductor Inc – 128, 256 and 1024 Channel CESoP Processors

ZL50110/11/14
Data Sheet
MII Port 3 - ZL50111 variant only
Note: This port must not be used to receive data at the same time as port 2,
they are mutually exclusive.
Signal
I/O
Package Balls
Description
M3_RXCLK
M3_COL
M3_RXD[3:0]
M3_RXDV
M3_RXER
M3_CRS
M3_TXCLK
M3_TXD[3:0]
M3_TXEN
M3_TXER
I U K26
MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
I D J26
Collision Detection. This signal is
independent of M3_TXCLK and
M3_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
I U [3] J22
[2] J23
[1] J24
[0] J25
Receive Data. Clocked on rising edge of
M3_RXCLK.
I D J21
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M3_RXCLK.
It is asserted when valid data is on the
M3_RXD bus.
I D H26
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M3_RXDV is asserted. Can be used
in conjunction with M3_RXD when
M3_RXDV signal is de-asserted to indicate
a False Carrier.
I D H24
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
I U H25
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz MII 100 Mbps
O [3] K23
[2] L26
[1] L25
[0] L24
Transmit Data. Clocked on rising edge of
M3_TXCLK.
O K24
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M3_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
O K25
Transmit Error. Transmitted synchronously
with respect to M3_TXCLK, and active high.
When asserted (with M3_TXEN also
asserted) the ZL50110/11/14 will transmit a
non-valid symbol, somewhere in the
transmitted frame.
Table 12 - MII Port 3 Interface Package Ball Definition (continued)
36
Zarlink Semiconductor Inc.