SP1648 Datasheet, PDF (7/7 Pages) Zarlink Semiconductor Inc – ECL OSCILLATOR

SP1648
For output frequency operation between 1MHz and
50MHz a 0.1µF capacitor is sufficient for C1 and C2. At
higher frequencies, smaller values of capacitance should be
used; at lower frequencies, larger values of capacitance. At
higher frequencies the value of bypass capacitors depends
directly upon the physical layout of the system. All by-
passing should be as close to the package pins as possible
to minimise unwanted lead inductance.
The peak-to-peak swing of the tank circuit is set
internally by the AGC circuitry. Since voltage swing of the
tank circuit provides the drive for the output buffer, the AGC
potential directly affects the output waveform. If it is desired
to have a sine wave at the output of the SP1648, a series
resistor is tied from the AGC point to the most negative
power potential (ground if +5.0V supply is used, -5.2V if a
negative supply is used).
At frequencies above 100MHz typ. it may be necessary
to increase the tank circuit peak-to-peak voltage in order to
maintain a square wave at the output of the SP1648. This is
accomplished by attaching a series resistor (1kΩ minimum)
from the AGC to the most positive power potential (+5.0V if a
+5.0V supply is used, ground if a -5.2V supply is used).
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© GEC Plessey Semiconductors 1994 Publication No. 3028 Issue No. 2.1 July 1994
TECHNICAL DOCUMENTATION - NOT FOR RESALE. PRINTED IN UNITED KINGDOM
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be
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