PDSP16540 Datasheet, PDF (6/11 Pages) Zarlink Semiconductor Inc – 32K BUCKET BUFFER

PDSP16540
tive data inputs into pre-defined blocks, which are then trans-
ferred to the rest of the system at the system clock rate.
All internal read and write operations are actually per-
formed by the continuous read strobe. When a write strobe is
received, internal syncronization occurs and the write opera-
tion is actually done with the read strobe. If data is being read
from the RAM when a write operation is requested, the read
sequence will be interupted for one read strobe period. The
flag indicating that data is available goes in-active for this
strobe period and the next system element should not accept
data during this perfiod.
The correct operation of the write synchronization circuit
requires that write operations occur at a slower rate than that
of the read strobe. In fact the write strobe period must be at
least twice the read strobe period plus some internal delays.
Table 1 gives the actual maximum writing rates, and shows
that the rate must be reduced when the block of data which is
read from the RAM is not completely composed of new data.
The maximum writing rate is limited by the need to have read
a complete block before the requested amount of new data
has been loaded.
A Data Available Flag is provided which goes active when
the pre-defined number of words have been written to the
RAM. The data read sequence then automatically starts and
the flag will go in-actice when the pre-programmed amount of
data has been read. An additional get ready to Read Me Flag
is provided which can separately be programmed to occur at
any point during the block write operation. This flag has no
internal action but can be used to warn the next system
element that data is to be expected.
DEFINING THE LENGTH OF THE BLOCKS
The amount of new data written to the RAM before the
Data Availble Flag is raised, and the amount of data which is
then read from the RAM are separately definable. In this way
the user can define the amount of old data which is re-read
before the new data will be accessed. These overlapping data
blocks are required in systems performing frequency domain
transforms, when a window operator is applied to prevent
frequency discontinuities between the blocks. The resulting
loss of information, caused by de-emphasizing the data near
the edges, is recovered by overlapping the blocks.
The mode control input MD0 is used to define the block
length during the read operation. When MD0 is tied low the
read block length will be 1024 words. When MD0 is tied high
the block length is defined by the state of pins D4:0, which
become inputs whilst the RESET input is active. A tri-state
buffer is needed on the outputs which is only enabled during
RESET, and whose inputs define the block length. These five
inputs allow the block length to be defined in multiples of 32
words, from a minimum of 32 up to the maximum of 1024. The
decode of the five bits (0 - 31) should be considered as defining
additional blocks of 32 words above the 32 word minimum.
The mode control inputs MD2:1 are used to define the
number of new words in the total block defined as above.
Decodes 0 through 2 define 1024, 512, and 256 new words
respectively. Decode 3 is used when a finer definition is
needed, and makes use of the states of pins D9:5 during reset.
The decodes of the five bits (0 - 31) then define additional
groups of 32 words above a 32 word minimum.
4
USING THE FLAGS
The data available flag (DAV) always goes active when
the required number of new words have been written to the
buffer, and the first word to be read is available at the output
pins. The rising edges of the read strobes must then be used
by the system to transfer the complete block of data to the next
system component. The minimum write periods given in Table
1 ensure that the first word will have been read before it is
replaced with new data.
Internal logic will increment the read address counter and
DAV will go in-active when the complete block has been read.
The DAV output will also go in-active for one read strobe
period every time a new word is written to the buffer. Write
operations to the next system component should be inhibited
for that cycle, and the DAV ouput must be used as write enable
for the next device. All DAV transitions are produced by the
rising edge of the read strobe.
An additional flag is provided which can be used to warn
the next system component that data is to be expected. This
get ready to read me flag (RMF) can be programmed to occur
at any point (within 16 words) during the write operation.
Decodes 0 through 2, from mode control inputs MD4:3, will
cause the flag to go active after 1024, 512, or 256 words
respectively have been loaded. Decode 3 allows the state of
pins D15:10 during RESET to be used to define the transition
point. Decodes 0 through 63 define form 0 to 63 additional
groups of 16 words after the minimum 16 words have been
loaded. The RMF flag goes in-active at the same time DAV
goes in-active.
The gap between the RMF and DAV outputs should be
sufficient to ensure that the next system component can
immediately accept data once DAV goes active. The RMF flag
has no internal action within the PDSP16540.
SUPPORTING THE PDSP16510
The PDSP16510 FFT Processor does not contain
sufficient RAM to allow it to perform continuous 1024 point
transforms without ignoring some of the incoming data. When
the PDSP16540 is used as an input buffer, continuous trans-
forms can be executed without any loss of information.
When block overlapping is not needed, or if the amount
is restricted to either 50% or 75%, the mode control inputs can
be directly used to define the operation of the PDSP16540.
The D15:0 pins need not be used to define the block lengths.It
should be noted, however, that the reset input is still needed
to initialise the device, even though the state of the D15:0 pins
is irelevent at that time. Figure 1 shows such a system.
Tying MD0 low defines the block length to be 1024 words,
and tying MD2:1 appropriately high or low will produce the
required decodes to provide 0%, 50%, or 75% overlaps. With
50% overlapping 512 new words are loaded, and with 75%
overlapping 256 new words are needed. MD5 should be tied
low unless real only transformsd are to be done (See the next
section).
The DAV output is used to drive the INEN input on the
PDSP16510 and the RMF flag is not used. The PDSDP16510
must be used in the mode in which INEN is an enabling signal,
rather than its edge activated mode (Control Register Bit 12
must be set). The LFLG transition produced by the
PDSP16510 is not used by the PDSP16540, since internal
logic computes the starting address for the read operation.