PDSP16540 Datasheet, PDF (5/11 Pages) Zarlink Semiconductor Inc – 32K BUCKET BUFFER

PDSP16540
N
D7
D8
D10
D12
D14
VDD
D17
GND
D19
D21
D23
D25
D26
M
D6
D9
D11
D13
D15
D16
D18
D20
D22
D24
D27
L
D4
D5
D28
D29
K
D2
D3
D30
D31
J
D0
D1
MD0
MD1
H
GND
RMF
MD2
GND
G
RS
WEN
MD3
MD4
F
VDD
DAV
MD5
VDD
E
WS
IP
0
D
IP
1
IP
2
C
IP
3
IP
4
B
IP
5
A
IP
6
IP
7
1
2
IP
31
RES
IP
IP
29
30
IP
IP
27
28
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
8
10
12
14
16
17
19
21
23
26
IP
IP
IP
IP
IP
IP
IP
IP
IP
9
11
13
VDD
15
GND
18
20
22
24
25
3
4
5
6
7
8
9
10
11
12
13
Pin Out Diagram - Bottom View (84pin PGA - AC84)
FUNCTIONAL DESCRIPTION
The PDSP16540 is designed for use in synchronous data
flow systems in which the transfer between system elements
is contolled by a continuously available system clock. This
system clock is usually at the maximum rate that the system
elements will allow, since it is governing the rate at which
processing can be performed on the acquired data. The rate
at which external data is actually inputed to the system ( the
sampling rate in DSP terminology ) is usually much slower
than the internal system, or computational, rate. The
PDSP16540 then provides a reservoir for data which is
acquired at the sampling rate and then processed with the
higher speed system clock rate.
Data is written to the RAM using an asynchronous write
strobe when a write enable input is active. The enbling signal
must meet the set up and hold times given in Table 1. Data is
read from the RAM using a read strobe which is expected to
be continuously availble and not to just go active when read
operations are actually needed. It is normally the high speed
system clock discussed earlier. All RAM addresses are
generated internally since the device is partitioning consecu-
3