MT90869 Datasheet, PDF (53/76 Pages) Zarlink Semiconductor Inc – Flexible 16K Digital Switch (F16kDX)

Data Sheet
MT90869
13.8.1
Local Output Advancement Bits 1-0 (LOA1-LOA0)
The binary value of these two bits is the amount of offset that a particular stream output can be advanced. When
the advancement is 0, the serial output stream has the normal alignment with the local frame pulse.
Local Output Advancement
Corresponding Advancement Bits
Clock Rate 131.072MHz
LOA1
LOA0
0 (Default)
0
0
-2 cycle
0
1
-4 cycles
1
0
-6 cycles
1
1
Table 28 - Local Output Advancement (LOAR) Programming Table
13.9
Backplane Output Advancement Registers (BOAR0 - 31)
Address 00A3h to 00C2h
Thirty-two Backplane Output Advancement Registers (BOAR0 to BOAR3) allow users to program the output
advancement for output data streams BSTo0 to BSTo31. For 2Mb/s, 4Mb/s, 8Mb/s and 16Mb/s stream operation
the possible adjustment is -2, -4 or -6 cycles of the internal system clock (131.072MHz). For 32Mb/ s stream
operation the possible adjustment is -1, -2 or -3 cycles of the internal system clock (131.072MHz). The BOAR0 to
BOAR3 registers are configured as follows:
BOARn Bit
(where n = 0 to 31 for non-32Mb/s
mode, n = 0 to 15 for 32Mb/s mode)
Name
Reset
Description
15-2
1:0
Reserved
BOA(1:0)
0
Reserved
0
Backplane Output Advancement Register
Table 29 - Backplane Output Advancement Register (BOAR) Bits
Zarlink Semiconductor Inc.
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