ZL50019 Datasheet, PDF (48/115 Pages) Zarlink Semiconductor Inc – Enhanced 2 K Digital Switch with Stratum 4E DPLL

ZL50019
24.0 Detailed Register Description
Data Sheet
External Read/Write Address: 0000_H
Reset Value: 0000_H
15 14
13
12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
SLV_ OPM OPM CKi_ FPIN CKINP FPINP CKIN CKIN VAR MBPE OSB MS1 MS0
DPLLEN
1
0
LP POS
1
0
EN
Bit
Name
Description
15 - 14 Unused Reserved. In normal functional mode, these bits MUST be set to zero.
13
SLV_ DPLL Enable in Slave Mode (ignored in Master Mode).
DPLLEN ^{When this bit is low, DPLL is disabled in Slave mode.}
When this bit is high and OSC_EN = 1, the DPLL is enabled in Slave mode.
When SLV_DPLLEN is set in Slave mode, CKo[3:0] and FPo[3:0] are generated from
CKi and FPi. CKo[5:4] and FPo[5] are locked to the selected input reference (one of
REF[3:0]). In this mode of operation, the DPLL retains its functionality, including the
generation of the REF_FAIL[3:0] output signals. See Table 7, “ZL50019 Operating
Modes” on page 36 for more details.
12 - 11 OPM1 - 0 Operation Mode.
These bits are used to set the device in Master/Slave operation. Refer to Table 7,
“ZL50019 Operating Modes” on page 36 for more details.
10
CKi_LP CKi and FPi Loopback (Ignored in Slave mode)
When this bit is low, CKi and FPi are used as input pins.
When this bit is high, CKi and FPi are internally looped back from CKo2 (16.384 MHz)
and FPo2 respectively, and CKi pin and FPi pin should be tied low or high externally;
CKIN1 - 0 (bits 6 - 5) of this register should be programmed to be 00. See Table 7,
“ZL50019 Operating Modes” on page 36 for more details.
9
FPINPOS Input Frame Pulse (FPi) Position
When this bit is low, FPi straddles frame boundary (as defined by ST-BUS).
When this bit is high, FPi starts from frame boundary (as defined by GCI-Bus)
8
CKINP Clock Input (CKi) Polarity
When this bit is low, the CKi falling edge aligns with the frame boundary.
When this bit is high, the CKi rising edge aligns with the frame boundary.
7
FPINP Frame Pulse Input (FPi) Polarity
When this bit is low, the input frame pulse FPi has the negative frame pulse format.
When this bit is high, the input frame pulse FPi has the positive frame pulse format.
6 - 5 CKIN1 - 0 Input Clock (CKi) and Frame Pulse (FPi) Selection
CKIN1 - 0
00
01
10
11
FPi Active Period
CKi
61 ns
122 ns
244 ns
16.384 MHz
8.192 MHz
4.096 MHz
Reserved
The MODE_4M0 and MODE_4M1 pins, as described in “Pin Description” on page 12,
should also be set to define the input clock mode.
Table 16 - Control Register (CR) Bits
48
Zarlink Semiconductor Inc.