MT90840 Datasheet, PDF (46/51 Pages) Mitel Networks Corporation – Distributed Hyperchannel Switch

MT90840
Data Sheet
AC Electrical Characteristics^† - Motorola Multiplexed Bus Mode
Voltages are with respect to ground (V_SS) unless otherwise stated.
Characteristics
Sym Min Typ^‡
Max Units
Test Conditions/
Notes
1 AS pulse width
2 Address setup from AS falling
3 Address hold from AS falling
4 Data setup from DTA LOW on
read
t_asw
10
t_ads
5
t_adh
5
t_ddr
0
5 CS hold after DS falling
t_csh
0
6 CS setup from DS rising
t_css
0
7 Data setup on write
t_dsw
10
8 Data hold after write
t_dhw
0
9 DS Inactive to AS Falling Edge
t_dss
23
10 R/W setup from DS rising
t_rws
5
11 R/W hold after DS falling
t_rwh
5
12 Data hold after read
t_dhr
10
15
13 DS delay after AS falling
t_dsh
15
14 Acknowledgment hold time
t_akh
0
15 Acknowledgment Delay:
Writing Registers
t_akd-wr
ns
ns
ns
ns C_L=150 pF on DTA,
30 pF on AD0-7.
ns
ns
ns
ns
ns
ns
22
ns C_L=30 pF
30
ns C_L=150 pF
ns
20
ns C_L=150 pF,
R_L=1kΩ∗
32
ns C_L=30 pF
41
ns C_L=150 pF
Acknowledgment Delay:
Reading Registers
t_akd-rd
16 Memory Acknowledgment Delay t_akd-mem
Reading TP Data Memory
244
488
Reading RP Data Memory
122
366
Reading TP Connection
Memory
1
clock
cycle
2 clock
cycles
Reading RP Connection
Memory
244
488
73
85
1306
1062
3 clk
cyc +
t_akd-rd
817
ns C_L=30 pF
ns C_L=150 pF
ns 1 to 5 C4 cycles +
register t_akd-rd
ns .5 to 4 C4 cycles +
register t_akd-rd
1 to 3 PCKT/R
cycles + register
t_akd-rd
ns 1 to 3 C4 cycles +
register t_akd-rd
Writing TP Connection
Memory**
Writing RP Connection
Memory**
t_akd-wr
t_akd-wr
3 clk
cyc +
t_akd-wr
774
Up to 3 PCKT/R
cyc. + register t_akd-wr
ns Up to 3 C4 cycles +
register t_akd-wr
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R_L, with timing corrected to cancel time taken to discharge C_L.
** Individual writes to Connection Memories will have Register Acknowledgment Delay. Burst writes to Connection Memories will have Read
Connection Memory Acknowledgment Delay.
2-276