ZL38001_06 Datasheet, PDF (31/49 Pages) Zarlink Semiconductor Inc – AEC for Analog Hands-Free Communication

ZL38001
Data Sheet
External Read/Write Address:21_H
Reset Value: 00_H
7
6
5
4
3
2
1
0
P-
ASC-
NLP-
INJ-
HPF-
HCLR
ADAPT-
ECBY
Bit
Name
Description
4
INJ-
When high, the Noise filtering process is disabled in the NLP and when low
the Noise filtering process is enabled.
3
HPF-
When high, Offset nulling filter is bypassed in the Sin/Sout path and when low
the Offset nulling filter in not bypassed.
2
HCLR
When high, Adaptive filter coefficients are cleared and when low the filter
coefficients are not cleared
1
ADAPT-
When high, the Echo canceller adaptation is disabled and when low the
adaptation is enabled.
0
ECBY
When high, the Echo estimate from the filter is not subtracted from the input
(Sin), when low the estimate is subtracted.
Register Table 2 - Acoustic Echo Canceller Control Register (AEC) (continued)
External Read/Write Address: 01_H
Reset Value: 00_H
7
6
5
4
3
2
1
0
SHFT
ASC-
NLP-
INJ-
HPF-
HCLR
ADAPT-
ECBY
Bit
Name
Description
7
SHFT
When high the 16-bit linear mode, inputs Sin, Rin, are shift right by 2 and
outputs Sout, Rout are shift left by 2. This bit is ignored when 16-bit linear
mode is not selected in both ports. This bit is also ignored if bit 7 of MC
register is set to zero.
6
ASC-
When high, the Internal Adaptation speed control is disabled and when low
the Adaptation speed is enabled.
5
NLP-
When high, the Non Linear Processor is disabled in the Rin/Rout path and
when low the NLP is enabled.
4
INJ-
When high, the Noise filtering process is disabled in the NLP and when low
the Noise filtering process is enabled.
3
HPF-
When high, Offset nulling filter is bypassed in the Rin/Rout path and when low
the Offset nulling filter in not bypassed.
2
HCLR
When high, Adaptive filter coefficients are cleared and when low the filter
coefficients are not cleared.
Register Table 3 - Line Echo Canceller Control Register (LEC)
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Zarlink Semiconductor Inc.