ZL38001_06 Datasheet, PDF (1/49 Pages) Zarlink Semiconductor Inc – AEC for Analog Hands-Free Communication

ZL38001
AEC for Analog Hands-Free
Communication
Data Sheet
Zarlink has introduced a new generation family of
AEC (ZL38002 and ZL38004). Zarlink recommends
these products for new designs.
Features
• Contains two echo cancellers: 112 ms acoustic
echo canceller + 16 ms line echo canceller
• Works with low cost voice codec. ITU-T G.711 or
signed mag µ/A-Law, or linear 2’s comp
• Each port may operate in different format
• Advanced NLP design - full duplex speech with
no switched loss on audio paths
• Fast re-convergence time: tracks changing echo
environment quickly
• Adaptation algorithm converges even during
Double-Talk
• Designed for exceptional performance in high
background noise environments
• Provides protection against narrow-band signal
divergence
• Howling prevention stops uncontrolled oscillation
in high loop gain conditions
• Offset nulling of all PCM channels
• Serial micro-controller interface
October 2006
Ordering Information
ZL38001DGA
ZL38001QDC
ZL38001QDG1
ZL38001DGF1
ZL38001DGE1
36 Pin QSOP
48 Pin TQFP
48 Pin TQFP*
36 Pin SSOP*
36 Pin SSOP*
Tubes
Trays
Trays, Bake & Drypack
Tape & Reel,
Bake & Drypack
Tubes, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
• ST-BUS, GCI, or variable-rate SSI PCM interfaces
• User gain control provided for speaker path
(-24 dB to +48 dB in 3 dB steps)
• 18 dB gain at Sout to compensate for high ERL
environments
• AGC on speaker path
• Handles up to 0 dB acoustic echo return loss
• Transparent data transfer and mute options
• 20 MHz master clock operation
• Low power mode during PCM Bypass
• Bootloadable for future factory software upgrades
• 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Sin
MD1
MD2
Rout
µ/A-Law/
Linear
Offset
Null
NBSD
+
+
-
S₁
Adaptive
Filter
R₃
Limiter
ADV
NLP
S₂
S₃
CONTROL
Program
RAM
Program
ROM
18dB
Gain
Linear/
µ/A-Law
Micro
Interface
UNIT
Double
Talk
Detector
Adaptive
Filter
Howling
Controller
NBSD
R₁
Linear/
µ/A-Law
R₂
-24 -> +21 dB
AGC
User
Gain
ADV
NLP
Limiter
-
+
+
Offset
Null
µ/A-Law/
Linear
VDD
VSS
RESET FORMAT ENA2
ENA1 LAW F0i BCLK/C4i MCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
Sout
DATA1
DATA2
SCLK
CS
Rin