ZL50233_06 Datasheet, PDF (30/38 Pages) Zarlink Semiconductor Inc – 4 Channel Voice Echo Cancellor

ZL50233
Data Sheet
Bit 7
Unused
Unused
MTDBI
MTDAI
Format
Law
PWUP
Bit 6
Main Control Register 1 (EC Group 1)
Power-up 00_hex
Bit 5
Bit 4
Bit 3
Bit 2
R/W Address: 401_hex
Bit 1
Bit 0
Unused
Unused
MTDBI
MTDAI
Format
Law
PWUP
Functional Description of Register Bits
Unused Bits.
Mask Tone Detector B Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
B is masked. The Tone Detector operates as specified in Echo Canceller B, Control Register 2.
When low, the Tone Detector B Interrupt is active.
Mask Tone Detector A Interrupt: When high, the Tone Detector interrupt output from Echo Canceller
A is masked. The Tone Detector operates as specified in Echo Canceller A, Control Register 2.
When low, the Tone Detector A Interrupt is active.
ITU-T/Sign Mag: When high, both Echo Cancellers A and B for a given group, select ITU-T (G.711)
PCM code. When low, both Echo Cancellers A and B for a given group, select sign-magnitude PCM
code.
A/µ Law: When high, both Echo Cancellers A and B for a given group, select A-Law companded
PCM code. When low, both Echo Cancellers A and B for a given group, select µ-Law companded
PCM code.
Power-UP: When high, both Echo Cancellers A and B and Tone Detectors for a given group, are
active. When low, both Echo Cancellers A and B and Tone Detectors for a given group, are placed
in Power Down mode. In this mode, the corresponding PCM data are bypassed from Rin to Rout
and from Sin to Sout with two frames delay. When the PWUP bit toggles from zero to one, the
echo cancellers A and B execute their initialization routine which presets their registers, Base
Address+00_hex to Base Address+3F_hex, to default Reset Value and clears the Adaptive Filter
coefficients. Two frames are necessary for the initialization routine to execute properly. Once the
initialization routine is executed, the user can set the per channel Control Registers for their specific
application.
Bit 7
IRQ
IRQ
Unused
Unused
I<4:0>
Interrupt FIFO Register
Power-up 00_hex
R/W Address: 410_hex
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
I4
I3
I2
I1
I0
Functional Description of Register Bits
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is
read. Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bit.
Unused bit.
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
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Zarlink Semiconductor Inc.