ZL30402 Datasheet, PDF (24/41 Pages) Zarlink Semiconductor Inc – SONET/SDH Network Element PLL

ZL30402
Data Sheet
Address: 28 H
Bit Name
Functional Description
7-5
RSV
Reserved.
4-3 InpFreq1-0 Input Frequency. These two bits identify the Secondary Reference Clock frequency.
- 00 = 19.44 MHz
- 01 = 8 kHz
- 10 = 1.544 MHz
- 11 = 2.048 MHz
2
RSV
Reserved.
1
SAH
Secondary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL
enters Holdover mode. Holdover mode is entered when reference frequency is:
- lost completely
- drifts more than ±30 000 ppm off the nominal frequency
- a large phase hit occurs on the reference clock.
0
SAFL Secondary Acquisition PLL Frequency Limit. This bit goes high whenever the Acquisition
PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large
excursion of still tolerable input jitter.
Table 17 - Secondary Acquisition PLL Status Register (R)
Address: 40 H
Bit
Name
Functional Description
Default
7-0 MCFC31 - 24 Master Clock Frequency Calibration. This most significant byte contains the
31st to 24th bit of the Master Clock Frequency Calibration Register. See
Applications section 4.2 for a detailed description of how to calculate the MCFC
value.
00000
000
Table 18 - Master Clock Frequency Calibration Register 4 (R/W)
Address: 41 H
Bit
Name
Functional Description
7-0
MCFC23 - 16 Master Clock Frequency Calibration. This byte contains the 23rd
to 16th bit of the Master Clock Frequency Calibration Register.
Table 19 - Master Clock Frequency Calibration Register 3 (R/W)
Default
00000
000
Address: 42 H
Bit
Name
Functional Description
Default
7-0
MCFC15 - 8 Master Clock Frequency Calibration. This byte contains the 15th 00000
to 8th bit of the Master Clock Frequency Calibration Register.
000
Table 20 - Master Clock Frequency Calibration Register 2 (R/W)
24
Zarlink Semiconductor Inc.