MT90870 Datasheet, PDF (24/86 Pages) Zarlink Semiconductor Inc – Flexible 12 k Digital Switch (F12kDX)

MT90870
Data Sheet
purposes of describing the device operation, the remaining part of this document assumes the ST-BUS style frame
pulse with a single width frame pulse of 122 ns and the C8IPOL bit is set to one unless explicitly stated otherwise.
In addition, the device provides FP8o, FP16o, C8o and C16o outputs to support external devices which connect to
the Local port. The Local frame pulses (FP8o, FP16o) will be provided in the same style as the master frame pulse
(FP8i). The polarity of C8o and C16o, at the Frame Boundary, can be controlled by the Control Register bit,
COPOL. An analogue phase lock loop (APLL) is used to multiply the external clock frequency to generate an
internal clock signal operated at 131.072 MHz.
2.4 Backplane Frame Pulse Input and Local Frame Pulse Output Alignment
The MT90870 accepts a Backplane Frame Pulse (FP8i) and generates the Local Frame Pulse outputs, FP8o and
FP16o, which are aligned to the master frame pulse. There is a constant three frame delay for data being switched.
Figure 8, Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s and 16 Mb/s,
shows the backplane and local frame pulse alignment for different data rates.
For further details of Frame Pulse conditions and options see Section 13.1, Control Register (CR), Figure 18,
Frame Boundary Conditions, ST- BUS Operation, and Figure 19, Frame Boundary Conditions, GCI - BUS
Operation.
FP8i
C8i
BSTi/BSTo0-31
(2 Mb/s)
BSTi/BSTo0-31
(4 Mb/s)
BSTi/BSTo0-31
(8 Mb/s)
BSTi/BSTo0-31
(16 Mb/s)
FP8o
C8o
LSTi/LSTo0-15
(2 Mb/s)
LSTi/LSTo0-15
(4 Mb/s)
LSTi/LSTo0-15
(8 Mb/s)
LSTi/LSTo0-15
(16 Mb/s)
CH0
CH1
CH2
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10 CH11
CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH
0
123 4
56 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CH0
CH1
CH2
CH0
CH1
CH2
CH3
CH4
CH5
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10 CH11
CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH CH
0
12 3 4
56 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Figure 8 - Backplane and Local Frame Pulse Alignment for Data Rates of 2 Mb/s, 4 Mb/s, 8 Mb/s
and 16 Mb/s
3.0 Input and Output Offset Programming
3.1 Input Channel Delay Programming (Backplane and Local Input Streams)
Various registers are used to control the input sampling point (delay) and the output advancement for the Local and
Backplane streams. The following sections explain the details of these offset programming features.
The control of the Input Channel Delay and the Input Bit Delay allows each input stream to have a different frame
boundary with respect to the master frame pulse, FP8i. By default, all input streams have channel delay of zero
such that Ch0 is the first channel that appears after the frame boundary.
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Zarlink Semiconductor Inc.