MT90870 Datasheet, PDF (1/86 Pages) Zarlink Semiconductor Inc – Flexible 12 k Digital Switch (F12kDX)

MT90870
Flexible 12 k Digital Switch (F12kDX)
Data Sheet
Features
• 12,288-channel x 12,288-channel non-blocking
unidirectional switching.The Backplane and
Local inputs and outputs can be combined to
form a non-blocking switching matrix with 48
stream inputs and 48 stream outputs
• 8,192-channel x 4,096-channel blocking
Backplane to Local stream switch
• 4,096-channel x 8,192-channel non-blocking
Local to Backplane stream switch
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
• 4,096-channel x 4,096-channel non-blocking
Local input to Local output stream switch
• Rate conversion on all data paths, Backplane to
Local, Local to Backplane, Backplane to
Backplane and Local to Local streams
• Backplane port accepts 32 ST-BUS streams with
data rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s
or 16.384 Mb/s in any combination, or a fixed
allocation of 16 streams at 32.768 Mb/s
November 2005
Ordering Information
MT90870AG 272 Ball PBGA
MT90870AG2 272 Ball PBGA*
Trays
Trays
*Pb Free Tin/Silver/Copper
-40 to +85^oC
*Note: the package thickness is different than the
MT90870AG (see drawing at the end of the data
sheet).
• Local port accepts 16 ST-BUS streams with data
rates of 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s or
16.384 Mb/s, in any combination
• Per-stream channel and bit delay for Local input
streams
• Per-stream channel and bit delay for Backplane
input streams
• Per-stream advancement for Local output streams
• Per-stream advancement for Backplane output
streams
V_{DD_IO} V_{DD_CORE} V_{SS (GND)}
RESET
ODE
BSTi0-31
BSTo0-31
BCST0-3
BORS
FP8i
C8i
Backplane
Interface
Backplane Data Memories
(8,192 channels)
Backplane
Connection Memory
(8,192 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
Local
Interface
Backplane
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Local
Timing
Unit
Test Port
LSTi0-15
LSTo0-15
LCST0-1
LORS
FP8o
FP16o
C8o
C16o
V_{DD_PLL}
DS CS R/W A14-A0 DTA D15-D0 TMS TDi TDo TCK TRST
Figure 1 - MT90870 Functional Block Diagram
1
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Copyright 2002-2005, Zarlink Semiconductor Inc. All Rights Reserved.