ZL50017_0611 Datasheet, PDF (23/51 Pages) Zarlink Semiconductor Inc – 1 K Digital Switch

ZL50017
Data Sheet
6.2 Constant Delay Mode
In this mode, frame integrity is maintained in all switching configurations. The delay though the switch is 2 frames -
Input Channel + Output Channel. This can result in a minimum of 1 frame + 1 channel delay if the last channel on a
stream is switched to the first channel of a stream. The maximum delay is 3 frames - 1 channel. This occurs when
the first channel of a stream is switched to the last channel of a stream. The constant delay mode is available for all
output channels.
The data throughput delay is expressed as a function of ST-BUS/GCI-Bus frames, input channel number (m) and
output channel number (n). The data throughput delay (T) is:
T = 2 frames + (n - m)
The constant delay mode is controlled by V/C (bit 14) in the Connection Memory Low when CMM = 0. When this bit
is set low, the channel is in constant delay mode. If VAREN (bit 4) in the Control Register (CR) is set (to enable
variable throughput delay on a chip-wide basis), the device can still be programmed to operate in constant delay
mode.
Frame N
Frame N + 1
Frame N + 2
STi L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
STio L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
STi L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
STio L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L-2 L-1 CH0 CH1 CH2 CH3
L = last channel = 31, 63, 127 or 255 for 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384 Mbps respectively.
Figure 13 - Data Throughput Delay for Constant Delay
7.0 Connection Memory Description
The connection memory consists of two blocks, Connection Memory Low (CM_L). The CM_L is 16 bits wide and is
used for channel switching and other special modes. Each connection memory location of the CM_L or CM_H can
be read or written via the 16 bit microprocessor port within one microprocessor access cycle. See Table 11 on
page 34 for the address mapping of the connection memory. Any unused bits will be reset to zero on the 16-bit data
bus.
For the normal channel switching operation, CMM (bit 0) of the Connection Memory Low (CM_L) is programmed
low. SCA7 - 0 (bits 8 - 1) indicate the source (input) channel address and SSA4 - 0 (bits 13 - 9) indicate the source
(input) stream address. When CMM (bit 0) of the Connection Memory Low (CM_L) is programmed high, the
ZL50017 will operate in one of the special modes described in Table 13 on page 36. When the per-channel
message mode is enabled, MSG7 - 0 (bit 10 - 3) in the Connection Memory Low (CM_L) will be output via the serial
data stream as message output data.
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Zarlink Semiconductor Inc.