ZL50017_0611 Datasheet, PDF (18/51 Pages) Zarlink Semiconductor Inc – 1 K Digital Switch

ZL50017
Data Sheet
5.1 Input Bit Delay Programming
The input bit delay programming feature provides users with the flexibility of handling different wire delays when
designing with source streams for different devices.
By default, all input streams have zero bit delay, such that bit 7 is the first bit that appears after the input frame
boundary (assuming ST-BUS formatting). The input delay is enabled by STIN[n]BD2-0 (bits 8 - 6) in the Stream
Input Control Register 0 - 15 (SICR0 - 15) as described in Table 9 on page 32. The input bit delay can range from 0
to 7 bits.
FPi
STi[n]
Bit Delay = 0
(Default)
STi[n]
Bit Delay = 1
Last Channel
Channel 0
Channel 1
Channel 2
432107654321076543210765432
Bit Delay = 1
Last Channel
Channel 0
Channel 1
Channel 2
543210765432107654321076543
Note: Last Channel = 31, 63, 127 and 255 for 2.048, 4.096, 8.192 and 16.384 Mbps modes respectively.
Figure 7 - Input Bit Delay Timing Diagram (ST-BUS)
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