ZL38010 Datasheet, PDF (2/27 Pages) Zarlink Semiconductor Inc – Low Power Quad ADPCM Transcoder

ZL38010
Data Sheet
Switching, on-the-fly, between 32 kbps and 24 kbps ADPCM, is possible by controlling the appropriate mode select
(MS1 - MS6) control pins. All optional functions of the device are pin selectable allowing a simple interface to
industry standard codecs, digital phone devices and Layer 1 transceivers. Linear coded PCM is provided to
facilitate external DSP functions.
Change Summary
Changes from October 2005 Issue to January 2007 Issue.
Page
1
Item
Change
Ordering Information Box Added Pb Free part numbers.
EN1 1
MCLK 2
F0i 3
C2o 4
BCLK 5
PCMo1 6
PCMi1 7
VSS ⁸
LINEAR ⁹
ENB2/F0od ¹⁰
ENB1 11
PCMo2 12
PCMi2 13
SEL 14
28 ^EN2
27 ^MS6
26 ^MS5
25 ^MS4
24 ^ADPCMo
23 ^ADPCMi
22 ^VDD
21 ^MS3
20 ^MS2
19 ^MS1
18 ^IC
17 PWRDN
16 FORMAT
15 A/µ
Pin Description
Pin #
Name
1
EN1
2
MCLK
3
F0i
4
C2o
Figure 2 - Pin Connections
Description
Enable Strobe 1 (Output). This 8 bit wide, active high strobe is active during the B1
PCM channel in ST-BUS mode. Becomes a single bit, high true pulse when LINEAR=1.
In SSI mode this output is high impedance.
Master Clock (input). This is a 4.096 MHz (minimum) input clock utilized by the
transcoder function; it must be supplied in both ST-BUS and SSI modes of operation.
In ST-BUS mode the C4 ST-BUS clock is applied to this pin. This synchronous clock is
also used to control the data I/O flow on the PCM and ADPCM input/output pins
according to ST-BUS requirements.
In SSI mode this master clock input is derived from an external source and may be
asynchronous with respect to the 8 kHz frame. MCLK rates greater than 4.096 MHz are
acceptable in this mode since the data I/O rate is governed by BCLK.
Frame Pulse (Input). Frame synchronization pulse input for ST-BUS operation. SSI
operation is enabled by connecting this pin to V_SS.
2.048 MHz Clock (Output). This ST-BUS mode bit clock output is the MCLK (C4) input
divided by two, inverted, and synchronized to F0i. This output is high-impedance during
SSI operation.
2
Zarlink Semiconductor Inc.