ZL38010 Datasheet, PDF (1/27 Pages) Zarlink Semiconductor Inc – Low Power Quad ADPCM Transcoder

ZL38010
Low Power Quad ADPCM Transcoder
Data Sheet
Features
• Full duplex transcoder with four encode channels
and four decode channels
• 32 kbps, 24 kbps and 16 kbps ADPCM coding
complying with ITU-T (previously CCITT) G.726
(without 40 kbps), and ANSI T1.303-1989
• Low power operation, 6.5 mW typical
• Asynchronous 4.096 MHz master clock operation
• SSI and ST-BUS interface options
• Transparent PCM bypass
• Transparent ADPCM bypass
• Linear PCM code
• No microprocessor control required
• Simple interface to Codec devices
• Pin selectable µ−Law or A-Law operation
• Pin selectable ITU-T or signed magnitude PCM
coding
• Single 3.3 Volts power supply
January 2007
Ordering Information
ZL38010DCE 28 Pin SOIC
ZL38010DCF 28 Pin SOIC
ZL38010DCE1 28 Pin SOIC**
ZL38010DCF1 28 Pin SOIC**
**Pb Free Matte Tin
-40°C to +85°C
Tubes
Tape & Reel
Tubes
Tape & Reel
Applications
• Pair gain
• Voice mail systems
• Wireless telephony systems
Description
The Quad ADPCM Transcoder is a low power, CMOS
device capable of four encode and four decode
functions per frame. Four 64 kbps PCM octets are
compressed into four 32, 24 or 16 kbps ADPCM words,
and four 32, 24 or 16 kbps ADPCM words are
expanded into four 64 kbps PCM octets. The 32, 24
and 16 kbps ADPCM transcoding algorithms utilized
conform to ITU-T Recommendation G.726 (excluding
40 kbps), and ANSI T1.303 - 1989.
ADPCMi
ADPCMo
ENB1
ENB2/F0od
BCLK
F0i
MCLK
C2o
EN1
EN2
Full Duplex
ADPCM
I/O
Quad
Transcoder
PCM
I/O
PCMo1
PCMi1
PCMo2
PCMi2
Timing
Control Decode
VDD VSS PWRDN IC
MS1 MS2 MS3 A/µ FORMAT MS4 MS5 MS6 LINEAR SEL
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved.