ZL50070 Datasheet, PDF (15/66 Pages) Zarlink Semiconductor Inc – 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs

ZL50070
Data Sheet
1.0 Functional Description
1.1 Overview
The device has 96 ST-BUS/GCI-Bus inputs (STiA0 - 23, STiB0 - 23, STiC0 - 23, STiD0 - 23) and 96
ST-BUS/GCI-Bus outputs (SToA0 - 23, SToB0 - 23, SToC0 - 23, SToD0 - 23). It is a non-blocking digital switch with
24,576 64 kbps channels and is capable of performing rate conversion between groups of 4 inputs and 4 outputs.
The inputs accept serial input data streams with data rates of 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or
65.536 Mbps. There are 24 input groups with each group consisting of 4 streams (‘A’, ‘B’, ‘C’ and ‘D’). Each group
can be set to any of the data rates. The outputs deliver serial data streams with data rates of 8.192 Mbps,
16.384 Mbps, 32.768 Mbps or 65.536 Mbps. There are 24 output groups with each group consisting of 4 streams
(‘A’, ‘B’, ‘C’ and ‘D’). Each group can be set to any of the data rates.
By using Zarlink’s message mode capability, the microprocessor can store data in the connection memory which
can be broadcast to the output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other ST-BUS/GCI-Bus devices.
The ZL50070 uses the ST-BUS/GCI-Bus master input frame pulse (FPi0) and the ST-BUS/GCI-Bus master input
clock (CKi0) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with
various data rates (8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps). The rate of the input clock is defined
by setting the CK_SEL1 - 0 pins. In addition, two more frame pulses and clocks can be accepted. The frequencies
of these signals are automatically detected by the ZL50070.
A selectable Motorola or Intel compatible non-multiplexed microprocessor port allows users to program the device
to operate in various modes under different switching configurations. Users can use the microprocessor port to
perform internal register and memory read and write operations. The microprocessor port can be selectable to be
either a 32 bit or 16 bit data bus and to have either a 19 bit or 17 bit address bus. This is selected by setting the
D16B pin. There are seven control signals (CS, DS, R/W, DTA, WAIT, BERR and IM).
The device supports the mandatory requirements for the IEEE1149.1 (JTAG) standard via the test port.
1.2 Switch Operation
The ZL50070 switches 64 kbps and Nx64 kbps data and voice channels from the TDM input streams, to timeslots
in the TDM output streams. The device is non-blocking; all 24 K input channels can be switched through to the
outputs. Any input channel can be switched to any available output channel.
Input Group 0
STiA0
STiB0
STiC0
STiD0
24 K x 24 K
SToA0
SToB0
SToC0
SToD0
Output Group 0
TDM INPUT
96 Streams
TDM OUTPUT
96 Streams
Input Group 23
STiA23
STiB23
STiC23
STiD23
SToA23
SToB23
SToC23
SToD23
Output Group 23
ZL50070
Figure 2 - 24 K x 24 K Channel Basic Switch Configuration
The maximum channel switching capacity is determined by the number of streams and their rate of operation, as
shown in Table 1.
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Zarlink Semiconductor Inc.