ZL50070 Datasheet, PDF (1/66 Pages) Zarlink Semiconductor Inc – 24 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 96 Inputs and 96 Outputs

ZL50070
24 K Channel Digital Switch with High Jitter
Tolerance, Rate Conversion per Group of
4 Streams (8, 16, 32 or 64 Mbps),
and 96 Inputs and 96 Outputs
Data Sheet
Features
January 2006
• 24,576 channel x 24,576 channel non-blocking
digital Time Division Multiplex (TDM) switch at
65.536 Mbps, 32.768 Mbps and 16.384 Mbps or
using a combination of rates
• 12,288 channel x 12,288 channel non-blocking
digital TDM switch at 8.192 Mbps
• High jitter tolerance with multiple input clock
sources and frequencies
• Up to 96 serial TDM input streams, divided into
24 groups with 4 input streams per group
• Up to 96 serial TDM output streams, divided into
24 groups with 4 output streams per group
• Per-group input and output data rate conversion
selection at 65.536 Mbps, 32.768 Mbps,
16.384 Mbps and 8.192 Mbps. Input and output
data group rates can differ
• Per-group input bit delay for flexible sampling
point selection
• Per-group output fractional bit advancement
• Four sets of output timing signals for interfacing
additional devices
• Per-channel A-Law/µ-Law Translation
Ordering Information
ZL50070GAC 484 Ball PBGA Trays
ZL50070GAG2 484 Ball PBGA** Trays
**Pb Free Tin/Silver/Copper
-40°C to +85°C
• Per-channel constant or variable throughput delay
for frame integrity and low latency applications
• Per-stream Bit Error Rate (BER) test circuits
• Per-channel high impedance output control
• Per-channel force high output control
• Per-channel message mode
• Control interface compatible with Intel and
Motorola Selectable 32 bit and 16 bit non-
multiplexed buses
• Connection Memory block programming
• Supports ST-BUS and GCI-Bus standards for
input and output timing
• IEEE 1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core
voltage
STiA0
STiB0
STiC0
ST_: iD0
:
STiA23
STiB23
STiC23
STiD23
FPi2-0
CKi2-0
CK_SEL1-0
FPo3-0
CKo3-0
VDD_CORE VDD_IO VSS
ODE PWR
S/P
Converter
Input
Timing
Data Memory
P/S
Converter
Connection Memory
Output
Timing
Timing
Microprocessor Interface
and Control Registers
Test Access
Port
SToA0
SToB0
SToC0
ST_:oD0
:
SToA23
SToB23
SToC23
SToD23
Figure 1 - ZL50070 Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.