ZL30406 Datasheet, PDF (15/21 Pages) Zarlink Semiconductor Inc – SONET/SDH Clock Multiplier PLL

ZL30406
Data Sheet
AC Electrical Characteristics^† - Output Timing Parameters Measurement Voltage Levels
Characteristics
Sym
CMOS^‡
LVPECL
CML
1 Threshold Voltage
2 Rise and Fall Threshold Voltage High
V_T-CMOS
V_T-LVPECL
V_T-CML
V_HM
0.5V_DD
0.7V_DD
0.5V_{OD_LVPECL}
0.8V_{OD_LVPECL}
0.5V_{OD_CML}
0.8V_{OD_CML}
Units
V
V
3 Rise and Fall Threshold Voltage Low
V_LM
0.3V_DD 0.2V_{OD_LVPECL} 0.2V_{OD_CML}
V
All Signals
Timing Reference Points
t_IF, t_OF
t_IR, t_OR
V_HM
V_T
V_LM
Figure 12 - Output Timing Parameter Measurement Voltage Levels
AC Electrical Characteristics^† - C19i Input to C19o and C77o Output Timing
Characteristics
Sym.
Min.
Typ.^‡
Max.
1 C19i to C19o delay
t_C19D
6.7
2 C19i to C77oA delay
t_C77D
-4
† Supply voltage and operating temperature are as per Recommended Operating Conditions.
‡ Typical figures are for design aid only: not guaranteed and not subject to production testing.
Units
ns
ns
Notes
C19i
(19.44 MHz)
C19o
(19.44 MHz)
C77oA
(77.76 MHz)
t_C19D
t_C77D
Note: All output clocks have nominal 50% duty cycle.
Figure 13 - C19i Input to C19o and C77o Output Timing
V_T-CMOS
V_T-CMOS
V_T-LVPECL
15
Zarlink Semiconductor Inc.