ZL30406 Datasheet, PDF (1/21 Pages) Zarlink Semiconductor Inc – SONET/SDH Clock Multiplier PLL

ZL30406
SONET/SDH Clock Multiplier PLL
Features
• Meets jitter requirements of Telcordia GR-253-
CORE for OC-48, OC-12, and OC-3 rates
• Meets jitter requirements of ITU-T G.813 for STM-
16, STM-4 and STM-1 rates
• Provides four LVPECL differential output clocks at
77.76 MHz
• Provides a CML differential clock programmable
to 19.44 MHz, 38.88 MHz, 77.76 MHz and
155.52 MHz
• Provides a single-ended CMOS clock at
19.44 MHz
• Provides enable/disable control of output clocks
• Accepts a CMOS reference at 19.44 MHz
• 3.3 V supply
Applications
• SONET/SDH line cards
• Network Element timing cards
Data Sheet
February 2005
Ordering Information
ZL30406QGC 64 Pin TQFP
ZL30406QGC1 64 Pin TQFP*
*Pb Free Matte Tin
-40°C to +85°C
Description
Trays
Trays
The ZL30406 is an analog phase-locked loop (APLL)
designed to provide rate conversion and jitter
attenuation for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30406 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-48, OC-12, OC-3, OC-1
rates and ITU-T G.813 STM-16, STM-4 and STM-1
rates.
The ZL30406 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 77.76 MHz, a CML differential
clock programmable to 19.44 MHz, 38.88 MHz,
77.76 MHz and 155.52 MHz and a single-ended
CMOS clock at 19.44 MHz. The output clocks can
be individually enabled or disabled.
C19i
BIAS
LPF
Frequency
& Phase
Detector
19.44MHz
Reference &
Bias circuit
Loop
Filter
VCO
C77oEN-A
C77oEN-B
OC-CLKoEN
C77o,C155o
C19o, C38o,
CML-P/N outputs
Output
Interface
Circuit
OC-CLKoP/N
C77oP/N-A
C77oP/N-B
C77oP/N-C
C77oP/N-D
C19o
VDD GND VCC
FS1-2
C19oEN
C77oEN-C
C77oEN-D
15
Figure 1 - Functional Block Diagram
1
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Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.