ZL30122 Datasheet, PDF (14/23 Pages) Zarlink Semiconductor Inc – SONET/SDH Low Jitter Line Card Synchronizer

ZL30122
Data Sheet
1.5 Output Clocks and Frame Pulses
The ZL30122 offers a wide variety of outputs including one low-jitter differential LVPECL clock (diff_clk_p/n), one
SONET/SDH LVCMOS (sdh_clk) output clock and one programmable LVCMOS (p_clk) output clock. In addition to
the clock outputs, one LVCMOS SONET/SDH frame pulse output (sdh_fp) and one LVCMOS programmable frame
pulse (p_fp) is also available.
DPLL
Programmable
Synthesizer
SONET/SDH
APLL
p_clk
p_fp
diff_clk_p/n
sdh_clk
sdh_fp
Figure 6 - Output Configuration
The supported frequencies for the output clocks and frame pulses are shown in Table 4.
diff_clk_p/n
(LVPECL)
6.48 MHz
19.44 MHz
38.88 MHz
51.84 MHz
77.76 MHz
155.52 MHz
311.04 MHz
622.08 MHz
sdh_clk
(LVCMOS)
6.48 MHz
p_clk
(LVCMOS)
2 kHz
9.72 MHz
12.96 MHz
19.44 MHz
25.92 MHz
38.88 MHz
51.84 MHz
77.76 MHz
N * 8 kHz (up to 77.76
MHz)
Table 4 - Output Clock and Frame Pulse Frequencies
sdh_fp, p_fp
(LVCMOS)
166.67 Hz
(48x 125 µs frames)
400 Hz
1 kHz
2 kHz
4 kHz
8 kHz
32 kHz
64 kHz
14
Zarlink Semiconductor Inc.