ZL30122 Datasheet, PDF (1/23 Pages) Zarlink Semiconductor Inc – SONET/SDH Low Jitter Line Card Synchronizer

ZL30122
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
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Features
• Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
• Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
• Programmable output synthesizer generates clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Digital Phase Locked-Loop (DPLL) provides all the
features necessary for generating SONET/SDH
compliant clocks including automatic hitless
reference switching, automatic mode selection
(locked, free-run, holdover), and selectable loop
bandwidth
Ordering Information
May 2006
ZL30122GGG 64 Pin CABGA
Trays
ZL30122GGG2 64 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40^oC to +85^oC
• Provides 3 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Provides 3 sync inputs for output frame pulse
alignment
• Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
• Configurable input to output delay, and output to
output phase alignment
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan
osco
osci
trst_b tck tdi tms tdo
Master
Clock
IEEE 1449.1
JTAG
ref0
ref2:0
ref1
ref2
sync0
sync1
sync2
sync2:0
Reference ^{ref_&_sync_status}
Monitors
dpll_lock dpll_holdover
diff_en
ref
DPLL
sync
SONET/SDH
APLL
Programmable
Synthesizer
diff_clk_p/n
sdh_clk
sdh_fp
p_clk
p_fp
int_b
SPI Interface
Controller &
State Machine
sck
si so cs_b
rst_b
dpll_mod_sel
sdh_filter filter_ref0 filter_ref1
Figure 1 - Block Diagram
1
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Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.