ZL30102_05 Datasheet, PDF (14/48 Pages) Zarlink Semiconductor Inc – T1/E1 Stratum 4/4E Redundant System Clock Synchronizer for DS1/E1 and H.110

ZL30102
Data Sheet
C20 Clock Accuracy
0 ppm
-130 -100
C20
0
100 130
Out of Range
In Range
+50 ppm
-80 -50
C20
50
150 180
Out of Range
In Range
-50 ppm
-180 -150
C20
-50
50 80
Out of Range
In Range
-200 -150 -100 -50 0
C20: 20 MHz master oscillator clock
50 100 150 200
Frequency offset [ppm]
Figure 6 - E1 Out-of-Range Thresholds for OOR_SEL=1
In addition to the monitoring of the REF2 reference signal the companion REF2_SYNC input signal is also
monitored for failure (see Figure 7).
Sync Ratio Monitor (SRM): This monitor detects if the REF2_SYNC signal is an 8 kHz signal. It also checks the
number of REF2 reference clock cycles in a single REF2_SYNC frame pulse period to determine the integrity of the
REF2_SYNC signal, for example there must be exactly 256 clock cycles of a 2.048 MHz REF2 reference clock in a
single REF2_SYNC 8 kHz frame pulse period to validate the REF2_SYNC signal. If the REF2 and REF2_SYNC
inputs are selected for synchronization and the Sync Ratio Monitor detects a failure, the DPLL will abandon the
mechanism of aligning the output frame pulse to the REF2_SYNC pulse. Instead only the REF2 reference will be
used for synchronization.
REF2_SYNC
REF2
REF2
frequency
SYNC
Reference
Monitor
Circuit
to DPLL
Figure 7 - REF2_SYNC Reference Monitor
3.3 Time Interval Error (TIE) Corrector Circuit
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
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Zarlink Semiconductor Inc.