MT91L62 Datasheet, PDF (11/19 Pages) Mitel Networks Corporation – ISO2-CMOS 3 Volt Single Rail Codec

MT91L62
Data Sheet
Electrical Characteristics^† for Analog Inputs
Characteristics
Sym.
1 Maximum input voltage without
overloading Codec
across AOUT+/AOUT-
V_IOLH
Min.
Typ.^‡
2.128
2.20
Max.
Units
Test Conditions
Vp-p A/µ = 0
Vp-p A/µ = 1
2 Input Impedance
Z_I
50
kΩ Ain+/Ain- to V_SS
† Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics^† - SSI BUS Synchronous Timing (see Figure 5)
Characteristics
Sym. Min. Typ.^‡ Max. Units
Test Conditions
1 BCL Clock Period
t_BCL 244
1953 ns BCL=4096 kHz to 512 kHz
2 BCL Pulse Width High
t_BCLH 115
122
ns BCL=4096 kHz
3 BCL Pulse Width Low
t_BCLL
122
ns BCL=4096 kHz
4 BCL Rise/Fall Time
t_R/t_F
20
ns Note 1
5 Strobe Pulse Width
t_ENW
8 x t_BCL
ns Note 1
6 Strobe setup time before BCL falling t_SSS 70
t_BCL-80 _ns
7 Strobe hold time after BCL falling
t_SSH
80
t_BCL-80 _ns
8 Dout High Impedance to Active Low t_DOZL
from Strobe rising
55
ns C_L=50 pF, R_L=1K
9 Dout High Impedance to Active High t_DOZH
from Strobe rising
55
ns C_L=50 pF, R_L=1K
10 Dout Active Low to High Impedance t_DOLZ
from Strobe falling
90
ns C_L=50 pF, R_L=1K
11 Dout Active High to High Impedance t_DOHZ
from Strobe falling
90
ns C_L=50 pF, R_L=1K
12 Dout Delay (high and low) from BCL t_DD
rising
80
ns C_L=50 pF, R_L=1K
13 Din Setup time before BCL falling
t_DIS
10
ns
14 Din Hold Time from BCL falling
t_DIH
50
ns
† Timing is over recommended temperature range & recommended power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.
11
Zarlink Semiconductor Inc.