ZL50052 Datasheet, PDF (10/59 Pages) Zarlink Semiconductor Inc – 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs

ZL50052
Data Sheet
Pin Description (continued)
Pin Name
ZL50052
Package
Coordinates
(196 ball
PBGA)
Description
FP16o
P12
Frame Pulse Output (5 V Tolerant Three-state Output)
When the Frame Pulse Width bit (FPW) of the Control Register is LOW
(default), this pin outputs a 61 ns-wide frame pulse. When the FPW bit is
HIGH, this pin outputs a 122 ns-wide frame pulse. The frame pulse, running
at 8 kHz rate, will have the same format (ST-BUS or GCI-Bus) as the input
frame pulse (FP8i). Output data on both the Backplane and Local sides
(BSTo0-7 and LSTo0-7) will be aligned to this frame pulse and the
accompanying output clock, C16o.
Backplane and Local Inputs
BSTi0-7
G1, H1, H2, H3,
J1, J2, K1, J3
Backplane Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal
Pull-downs)
These pins accept serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
LSTi0-7
K14, J13, J14,
K13, M14, J12,
L14, M13
Local Serial Input Streams 0 to 7 (5 V Tolerant Inputs with Internal
Pull-downs)
These pins accept serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
Backplane and Local Outputs and Control
ODE
B9
Output Drive Enable (5 V Tolerant Input with Internal Pull-up)
An asynchronous input providing Output Enable control to the BSTo0-7 and
LSTo0-7 outputs.
When LOW, the BSTo0-7 and LSTo0-7 outputs are driven HIGH or high
impedance (dependent on the BORS and LORS pin settings respectively).
When HIGH, the outputs BSTo0-7 and LSTo0-7 are enabled.
BORS
G2
Backplane Output Reset State (5 V Tolerant Input with Internal
Pull-down)
When this input is LOW, the device will initialize with the BSTo0-7 outputs
driven high. Following initialization, the Backplane stream outputs are always
active.
When this input is HIGH, the device will initialize with the BSTo0-7 outputs at
high impedance. Following initialization, the Backplane stream outputs may
be set active or high impedance using the ODE pin or on a per-channel basis
with the BE bit in the Backplane Connection Memory.
BSTo0-7
B3, A1, A2, C4,
C5, B2, D2, C2
Backplane Serial Output Streams 0 to 7 (5 V Tolerant, Three-state
Outputs with Slew-Rate Control)
These pins output serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
Refer to the descriptions of the BORS and ODE pins for control of the output
HIGH or high impedance state.
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Zarlink Semiconductor Inc.