ZL50052 Datasheet, PDF (1/59 Pages) Zarlink Semiconductor Inc – 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (32 Mbps), and 16 Inputs and 16 Outputs

ZL50052
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (32 Mbps),
and 16 Inputs and 16 Outputs
Data Sheet
Features
• 8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 16 input
streams and 16 output streams
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
• Backplane port accepts 8 input and 8 output ST-
BUS streams with data rate of 32.768 Mbps
• Local port accepts 8 input and 8 output ST-BUS
streams with data rate of 32.768 Mbps
• Exceptional input clock jitter tolerance (14 ns)
• Per-stream bit delay for Local and Backplane
input streams
• Per-stream advancement for Local and
Backplane output streams
December 2003
Ordering Information
ZL50052GAC 196 ball PBGA
-40°C to +85°C
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
• Per-channel message mode for Local and
Backplane output streams
• Connection memory block programming for fast
device initialization
• Automatic selection between ST-BUS and GCI-
Bus operation
• Non-multiplexed Motorola microprocessor
interface
V_{DD_IO} V_{DD_CORE}
V_{SS (GND)}
RESET
ODE
BSTi0-7
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-7
BSTo0-7
Backplane
Interface
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
LSTo0-7
BORS
FP8i
C8i
Input
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LORS
FP8o
FP16o
C8o
C16o
V_{DD_PLL}
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50052 Functional Block Diagram
1
Zarlink Semiconductor Inc.
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Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.