MT8986 Datasheet, PDF (1/46 Pages) Mitel Networks Corporation – CMOS ST-BUS™ FAMILY Multiple Rate Digital Switch

CMOS ST-BUS^TM Family
MT8986
Multiple Rate Digital Switch
Data Sheet
Features
• 256 x 256 or 512 x 256 switching configurations
• 8-bit or 4-bit channel switching capability
• Guarantees frame integrity for wideband
channels
• Automatic identification of ST-BUS/GCI interfaces
• Accepts serial streams with data rates up to
8.192 Mb/s
• Rate conversion from 2.048 Mb/s to 4.096 or
8.192 Mb/s and vice-versa
• Programmable frame offset on inputs
• Per-channel three-state control
• Per-channel message mode
• Control interface compatible to Intel/Motorola
CPUs
• Low power consumption
Applications
• Medium size digital switch matrices
• Hyperchannel switching (e.g., ISDN H0)
• MVIP^™ interface functions
• Serial bus control and monitoring
• Centralized voice processing systems
• Voice/Data multiplexer
• 32 kbit/s channel switching
February 2005
Ordering Information
MT8986AE
MT8986AP
MT8986AL
MT8986APR
MT8986AP1
MT8986APR1
40 Pin PDIP
44 Pin PLCC
44 Pin MQFP
44 Pin PLCC
44 Pin PLCC*
44 Pin PLCC*
*Pb Free Matte Tin
Tubes
Tubes
Trays
Tape & Reel
Tubes
Tape & Reel
-40°C to +85°C
Description
The Multiple Rate Digital Switch (MRDX) is an
upgraded version of Zarlink's MT8980D Digital Switch
(DX). It is pin compatible with the MT8980D and
retains all of its functionality. This device is designed to
provide simultaneous connections (non-blocking) for
up to 256 64 kb/s channels or blocking connections for
up to 512 64 kb/s channels. The serial inputs and
outputs connected to MT8986 may have 32 to 128
64 kb/s channels per frame with data rates ranging
from 2048 up to 8192 kb/s. The MT8986 provides per-
channel selection between variable and constant
throughput delays allowing voice and grouped data
channels to be switched without corrupting the data
sequence integrity.
In addition, the MT8986 can be used for switching of
32 kb/s channels in ADPCM applications. The MT8986
is ideal for medium size mixed voice and data
switching/processing applications.
V_DD V_SS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
* STi10
* STi11
* STi12
* STi13
* STi14
* STi15
Serial
to
Parallel
Converter
Multiple Buffer Data
Memory
Timing
Unit
Internal Registers
Microprocessor
Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8 *
STo9 *
* 44 Pin only
CLK FR AS/ IM DS _{CS R/W} A0/ _DTA AD7/
ALE * _RD
WR ^A7
AD0
CSTo
Figure 1 - Functional Block Diagram
1
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Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.